Rev. 1.71 100 April 11, 2017 Rev. 1.71 101 April 11, 2017
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
• SADC2 Register
Bit 7 6 5 4 3 2 1 0
Name ENOPA VBGEN — — SAVRS3 SAVRS2 SAVRS1 SAVRS0
R/W R/W R/W — — R/W R/W R/W R/W
POR 0 0 — — 0 0 0 0
Bit7 ENOPA:OPAenable/disablecontrolregister
0:OPAdisable
1:OPAenable
Bit6 VBGEN:Bandgapbufferdisable/enablecontrolbit
0:Bandgapbufferdisable
1:Bandgapbufferenable
Bit5~4 Unimplemented,readas"0"
Bit3~0 SAVRS3~SAVRS0:ADCreferencevoltageselectionbit
0000:ADCreferencevoltagecomesfromAV
DD
0001:ADCreferencevoltagecomesfromV
REF
0010:ADCreferencevoltagecomesfromV
REF
×2
0011:ADCreferencevoltagecomesfromV
REF
×3
0100:ADCreferencevoltagecomesfromV
REF
×4
1001:Inhibittouse
1010:ADCreferencevoltagecomesfromV
BG
×2
1011:ADCreferencevoltagecomesfromV
BG
×3
1100:ADCreferencevoltagecomesfromV
BG
×4
OtherValues:sameas0000
Note:(1)WhenSelectV
REF
orV
REF
×2orV
REF
×3orV
REF
×4asADCreferencevoltage,
HT66F002/HT66F0025:pinsharecontrolbits(PAS3,PAS2)is(1,0)toselectVREFasinput.
HT66F003:pinsharecontrolbits(PAS2,PAS1)is(1,0)toselectVREFasinput.
HT66F004:pinsharecontrolbits(PAS3,PAS2)is(1,0)toselectVREFasinput
(2)V
BG
=1.04V
(3)WhenSAVRS3=1,OPAselectsV
BG
asinput.
(4)IftheprogramsselectexternalreferencevoltageV
REF
andtheinternalreference
voltageV
BG
asADCreferencevoltage,thenthehardwarewillonlychoosetheinternal
referencevoltageV
BG
asanADCreferencevoltageinput.
A/D Operation
TheSTARTbitisusedtostartandresettheA/Dconverter.Whenthemicrocontrollersetsthisbit
fromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbeinitiated.When
theSTARTbitisbroughtfromlowtohighbutnotlowagain,theADBZbitintheSADC0register
willbeclearedtozeroandtheanalogtodigitalconverterwillbereset.ItistheSTARTbitthatis
usedtocontroltheoverallstartoperationoftheinternalanalogtodigitalconverter.
TheADBZbitintheSADC0registerisusedtoindicatewhethertheanalogtodigitalconversion
processisinprocessornot.WhentheA/DconverterisresetbysettingtheSTARTbitfrom
lowtohigh,theADBZagwillbeclearedto0.Thisbitwillbeautomaticallysetto“1”bythe
microcontrollerafteranA/Dconversionissuccessfullyinitiated.WhentheA/Dconversionis
complete,theADBZwillbeclearedto0.Inaddition,thecorrespondingA/Dinterruptrequestag
willbesetintheinterruptcontrolregister,andiftheinterruptsareenabled,anappropriateinternal
interruptsignalwillbegenerated.ThisA/Dinternalinterruptsignalwilldirecttheprogramowto
theassociatedA/Dinternalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled,
themicrocontrollercanbeusedtopolltheADBZbitintheSADC0registertocheckwhetherithas
beenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.