Rev. 1.71 18 April 11, 2017 Rev. 1.71 19 April 11, 2017
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
System Architecture
Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed
totheirinternalsystemarchitecture.Thedevicetakesadvantageoftheusualfeaturesfoundwithin
RISCmicrocontrollersprovidingincreasedspeedofoperationandPeriodicperformance.The
pipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstructionexecution
areoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withtheexceptionofbranch
orcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionsetoperations,which
carriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,
etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulatorandtheALU.
CertaininternalregistersareimplementedintheDataMemoryandcanbedirectlyorindirectly
addressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditionalarchitectural
featuresensurethataminimumofexternalcomponentsisrequiredtoprovideafunctionalI/Oand
A/Dcontrolsystemwithmaximumreliabilityandexibility.Thismakesthesedevicessuitablefor
low-cost,high-volumeproductionforcontrollerapplications
Clocking and Pipelining
Themainsystemclock,derivedfromeitheraHIRCorLIRCoscillatorissubdividedintofour
internallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthe
beginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4
clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleforms
oneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutive
instructioncycles,thepipeliningstructureofthemicrocontrollerensuresthatinstructionsare
effectivelyexecutedinoneinstructioncycle.Theexceptiontothisareinstructionswherethe
contentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasethe
instructionwilltakeonemoreinstructioncycletoexecute.
System Clock and Pipelining