Holtek HT66F002 - Entering the SLEEP1 Mode; Entering the IDLE0 Mode; Entering the IDLE1 Mode

Rev. 1.71 44 April 11, 2017 Rev. 1.71 45 April 11, 2017
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Entering the SLEEP1 Mode
ThereisonlyonewayforthedevicestoentertheSLEEP1Modeandthatistoexecutethe“HALT”
instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andthe
WDTon.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwill
occur:
•
ThesystemclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopat
the“HALT”instruction,buttheWDTwillremainwiththeclocksourcecomingfromthef
LIRC

clock.
•
TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheWDTwillbeclearedandresumecountingiftheWDTisenabled.
•
TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownag,PDF,willbesetandtheWatchdogtime-outag,TO,
willbecleared.
Entering the IDLE0 Mode
ThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe“HALT”
instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andthe
FSYSONbitinSMOD1registerequalto“0”.Whenthisinstructionisexecutedundertheconditions
describedabove,thefollowingwilloccur:
• Thesystemclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruc-
tion,buttheTimeBaseclockwillbeon.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheWDTwillbeclearedandresumecountingiftheWDTisenabled.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownag,PDF,willbesetandtheWatchdogtime-outag,TO,
willbecleared.
Entering the IDLE1 Mode
ThereisonlyonewayforthedevicestoentertheIDLE1Modeandthatistoexecutethe“HALT”
instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andthe
FSYSONbitinSMOD1registerequalto“1”.Whenthisinstructionisexecutedundertheconditions
describedabove,thefollowingwilloccur:
• ThesystemclockandTimeBaseclockwillbeonandtheapplicationprogramwillstopatthe
“HALT”instruction.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheWDTwillbeclearedandresumecountingiftheWDTisenabled.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownag,PDF,willbesetandtheWatchdogtime-outag,TO,
willbecleared.