Holtek HT66F002 - Conversion Rate and Timing Diagram

Rev. 1.71 102 April 11, 2017 Rev. 1.71 103 April 11, 2017
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Conversion Rate and Timing Diagram
AcompleteA/Dconversioncontainstwoparts,datasamplinganddataconversion.Thedata
samplingwhichisdenedast
ADS
takes4A/Dclockcyclesandthedataconversiontakes12A/D
clockcycles.Thereforeatotalof16A/DclockcyclesforanA/Dconversionwhichisdenedast
ADC

arenecessary.
MaximumsingleA/Dconversionrate=A/Dclockperiod/16
However,thereisausagelimitationonthenextA/Dconversionafterthecurrentconversionis
complete.WhenthecurrentA/Dconversioniscomplete,theconverteddigitaldatawillbestored
intheA/DdataregisterpairandthenlatchedafterhalfanA/Dclockcycle.IftheSTARTbitisset
to1inhalfanA/DclockcycleaftertheendofA/Dconversion,theconverteddigitaldatastored
intheA/Ddataregisterpairwillbechanged.Therefore,itisrecommendedtoinitiatethenextA/D
conversionafteracertainperiodgreaterthanhalfanA/Dclockcycle attheendofcurrentA/D
conversion.
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 
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  
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 
 
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  
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 
 
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  
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 
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 
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
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 
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 
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    
   
A/D Conversion Timing