Holtek HT66F002 - Page 127

Rev. 1.71 126 April 11, 2017 Rev. 1.71 127 April 11, 2017
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
CALL addr
 Subroutinecall
Description Unconditionallycallsasubroutineatthespeciedaddress.TheProgramCounterthen
 incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe
 stack.Thespeciedaddressisthenloadedandtheprogramcontinuesexecutionfromthis
 newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.
Operation Stack←ProgramCounter+1
 ProgramCounter←addr
Affectedag(s) None
CLR [m]
 ClearDataMemory
Description EachbitofthespeciedDataMemoryisclearedto0.
Operation [m]←00H
Affectedag(s) None
CLR [m].i
ClearbitofDataMemory
Description BitiofthespeciedDataMemoryisclearedto0.
Operation [m].i←0
Affectedag(s) None
CLR WDT
 ClearWatchdogTimer
Description TheTO,PDFagsandtheWDTareallcleared.
Operation WDTcleared
 TO←0
 PDF←0
Affectedag(s) TO,PDF
CLR WDT1
 Pre-clearWatchdogTimer
Description TheTO,PDFagsandtheWDTareallcleared.Notethatthisinstructionworksin
 conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave
 effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will
 havenoeffect.
Operation WDTcleared
 TO←0
 PDF←0
Affectedag(s) TO,PDF
CLR WDT2
 Pre-clearWatchdogTimer
Description TheTO,PDFagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction
 withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect.
 RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno
 e
ffect.
Operation WDTcleared
 TO←0
 PDF←0
Affectedag(s) TO,PDF
CPL [m]
ComplementDataMemory
Description EachbitofthespeciedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich
 previouslycontaineda1arechangedto0andviceversa.
Operation [m]←[m]
Affectedag(s) Z