Holtek HT66F002 - SMOD1 Register

Rev. 1.71 40 April 11, 2017 Rev. 1.71 41 April 11, 2017
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Bit4 Unimplemented,readas"0"
Bit3 LTO:Lowspeedsystemoscillatorreadyag
0:Notready
1:Ready
Thisisthelowspeedsystemoscillatorreadyagwhichindicateswhenthelowspeedsystem
oscillatorisstableafterpoweronresetorawake-uphasoccurred.Theagwillbelowwhenin
theSLEEP0mode,butafterawake-uphasoccurredtheagwillchangetoahighlevelafter1~2
cyclesiftheLIRCoscillatorisused.
Bit2 HTO:Highspeedsystemoscillatorreadyag
0:Notready
1:Ready
Thisisthehighspeedsystemoscillatorreadyagwhichindicateswhenthehighspeedsystem
oscillatorisstable.Thisagisclearedto“0”byhardwarewhenthedeviceispoweredonand
thenchangestoahighlevelafterthehighspeedsystemoscillatorisstable.Thereforethisag
willalwaysbereadas“1”bytheapplicationprogramafterdevicepower-on.
Bit1 IDLEN:IDLEModeControl
0:Disable
1:Enable
ThisistheIDLEModeControlbitanddetermineswhathappenswhentheHALTinstructionis
executed.Ifthisbitishigh,whenaHALTinstructionisexecutedthedevicewillentertheIDLE
Mode.IntheIDLE1ModetheCPUwillstoprunningbutthesystemclockwillcontinuetokeep
theperipheralfunctionsoperational,ifFSYSONbitishigh.IfFSYSONbitislow,theCPUand
thesystemclockwillallstopinIDLE0mode.IfthebitislowthedevicewillentertheSLEEP
ModewhenaHALTinstructionisexecuted.
Bit0 HLCLK:SystemClockSelection
0:f
H
/2~f
H
/64orf
L
1:f
H
Thisbitisusedtoselectifthef
H
clockorthef
H
/2~f
H
/64orf
L
clockisusedasthesystemclock.
Whenthebitishighthef
H
clockwillbeselectedandiflowthef
H
/2~f
H
/64orf
L
clockwillbe
selected.Whensystemclockswitchesfromthef
H
clocktothef
L
clockandthef
H
clockwillbe
automaticallyswitchedofftoconservepower.
SMOD1 Register
Bit 7 6 5 4 3 2 1 0
Name FSYSON — — — D3 LVRF — WRF
R/W R/W — — — R/W R/W — R/W
POR 0 — — — 0 x — 0
“x” unknown
B
it7 FSYSON:f
SYS
ControlinIDLEMode
0:Disable
1:Enable
Bit6~4 Unimplemented,readas0
Bit3 D3:Reservedbit
Bit2 LVRF:LVRfunctionresetag
0:Notactive
1:Active
Thisbitcanbeclearto“0”,butcannotbesetto“1”.
Bit1 Unimplemented,readas0