Holtek HT66F002 - Watchdog Time-out Reset during Normal Operation; Watchdog Time-out Reset during SLEEP or IDLE Mode

Rev. 1.71 52 April 11, 2017 Rev. 1.71 53 April 11, 2017
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
• SMOD1 Register
Bit 7 6 5 4 3 2 1 0
Name FSYSON — — — D3 LVRF — WRF
R/W R/W — — — R/W R/W — R/W
POR 0 — — — 0 x — 0
“x” unknown
B
it7 FSYSON:f
SYS
ControlinIDLEMode
Describeelsewhere
Bit6~4 Unimplemented,readas0
Bit3 D3:Reservedbit
Bit2 LVRF:LVRfunctionresetag
0:Notactive
1:Active
Thisbitcanbeclearto“0”,butcannotbesetto“1”.
Bit1 Unimplemented,readas0
Bit0 WRF:WDTControlregistersoftwareresetag
Describeelsewhere
Watchdog Time-out Reset during Normal Operation
TheWatchdogtime-outResetduringnormaloperationisthesameasanLVRresetexceptthatthe
Watchdogtime-outagTOwillbesetto“1”.

  


 
    
Note:t
RSTD
ispower-ondelay,typicaltime=16.7ms
WDT Time-out Reset during Normal Operation Timing Chart
Watchdog Time-out Reset during SLEEP or IDLE Mode
TheWatchdogtime-outResetduringSLEEPorIDLEModeisalittledifferentfromotherkinds
ofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStack
Pointerwillbeclearedto“0”andtheTOagwillbesetto“1”.RefertotheA.C.Characteristicsfor
t
SST
details.
 
 
    
WDT Time-out Reset during SLEEP or IDLE Timing Chart