A4 AUTOMATIC LEVELING CONTROL (ALC), CIRCUIT DESCRIPTION (CHANGE
8)
The A4 Automatic Leveling Control (ALC) assembly is part of a closed loop power leveling
function, designed to control the amplitude
ofthe RF output power. The General section below
describes loop operation, including some components external to the A4 assembly. The rest of
this operational theory is devoted to detailed description of the circuits found on the A4
assembly.
General
The circuits which accomplish power control and power leveling can
be
divided into two
categories: internal loop circuitry, and external components of the loop. Figure 8-25 illustrates
this theme.
The Power Level Reference leg of the ALC establishes the desired power level. This is accom-
plished by pressing the plug-in
[POWER LEVEL] pushbutton and rotating the RPG or entering
the desired reference on the Model
8350A/B front panel DATA ENTRY keys. This leg of the
ALC is not an interdependent part of the loop, as shown in Figure 8-25.
The Detector leg of the ALC loop samples the actual RF output power and produces a voltage
proportional to RF amplitude. This voltage is converted to log scale and compared with the
Power Level Reference signal. If the voltages at the summing junction are not of equal
magnitude
an error voltage is generated. This error voltage is amplified and converted to a
current drive for the RF modulators, which vary the transmitted RF power to correct the error
and achieve the desired RF power level.
Address Decoder and Control Latches A
U12 is a 3-to-8 decoder, selecting address 2C07H when it is present on the address bus. This
address serves as a chip enable for octal latch U13. Information on the data bus is then latched
into U13 and used throughout the A4 assembly. U14 and
U15 have been added to provide the
proper outputs for all 3 ALC leveling modes.
Detector Inputs and Selection Switches
B
Control lines MUX AOB and MUX AlB are encoded with leveling mode and band selection
information. The lines are decoded in Table 8-10. U6 decodes these control lines to select the
proper detector input for the desired operating mode.
R43 and R14 BIAS adjustment offset the Band
0 internal detector so that
0
volts at TP7
corresponds to no RF power.
EXT/MTR ALC input provides external crystal leveling capability within the
-
10
to
-
200
mV
range and power meter leveling capability within the
0
to
+
1V range. VR4 and VR5 provide
protection against transients. Two Schottky diodes,
CRl and CR2, are mounted between the
EXT/MTR ALC connector and the front panel casting for similar protection.
When
MTR (power meter) leveling is selected, the power meter (HP 432A/B/C, 436A, or 438A)
is used in conjunction with the internal leveling detector. UlA routes the power meter signal to a
separate POWER METER LOG AMPLIFIER. The internal leveling detector is routed through
U6B and the input sample and hold to the main log amplifier. The internal leveling detector
compensates for the response of the power meter and prevents instability while at the same time
permitting reasonable sweep times.
CHANGE
8
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