A4 (ALC), CIRCUIT DESCRIPTION (CHANGE 8)(Cont9d)
U6A decodes MUX AOB and MUX AlB (Table 8-10) to select the proper offset voltage for power
calibration at the low end of the plug-in power range. In
EXTernal ALC, the power level
calibration is set with the front panel EXT CAL potentiometer.
U18 amplifies the logged output for comparison with the Power Level Summing Signal
(Block
H).
R9 adjusts the gain of U18, and calibrates midrange power level.
Guarded-gate
FETs 47, Q8 and 416 select the appropriate detector return for INTernal,
EXTernal, and PM (power meter) leveling.
Power Level Reference
C
Power Level Summing H
Ul1 is a 12-bit microprocessor-compatible digital to analog converter (DAC), which latches data
in three 4-bit nibbles. The
-
10V
REF
input sets the DAC for a maximum outut (TP2) of
+
10V.
The voltage at TP2 is the product of
-
10V
REF
and the fractional binary input of the DAC.
The voltage at
TPl is the sum of several voltages, depending on the operating mode of the plug-
in. U2A sums PWR
SWP/COMP and AM inputs. In addition, selected feedback resistor
R7
reduces gain to compensate for detector deviation from square-law at the upper limits of the
plug-in power range.
The EXT CAL input is summed through amplifier
U2C. R30, in the feedback loop of U2C,
provides temperature compensation for the Log Amplifier and detectors.
Error, Sample and Hold
I
The Error, Sample and Hold function prevents the Main ALC Amp from saturating during pulse
and square wave modulation.
U2D pin 10 is the summing junction for the Power Level Summing output, Log Amplifier
output, and FREQ TRK
V
is a 0 to
+6
volt ramp proportional to the
YO
DRIVE Voltage. R1
(SLP) adjusts the overall flatness.
Under leveled power conditions, the voltage at U2D pin 10 is zero. A non-zero voltage
represents an error and forces a change in modulator current until power is again level.
U2D buffers the error voltage. Q5 and the following integrating circuit (U9) perform the sample
and hold. C7 eliminates error due to the gate to source capacitance of
Q5.
Log Amplifier Selector
J
The Log Amplifier Selector circuit selects through path for the Log Amplifier, or combines its
output with that of the Power Meter Log Amplifier (MTR). In
MTR,
R84 and C3 act as a high
pass filter, to shape the output of the Log Amplifier, which is then combined with the Power
Meter Log Amplifier output. The combination of the two prevents instability when using certain
power meters.
In switch U4: A and B are open, C is closed in INT or EXT DET mode. The opposite is true
in
MTR mode.
CHANGE
8
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