Service
Model 83522A
Troubleshooting Diagnostics
The troubleshooting information below is organized into functional areas:
Digital Control
@
-
Reference Power Level
@
@
DetectorlDetector Selection Switch
@
DCl
Detector Leg
@
@
Modulator Leg
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@
Mod Driver
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Digital Control
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Address Decoder U12 and Control Latch U13 control digital switches
throughout the A4 assembly. Their operation can be confirmed by performing
the Hex Data Rotation Write at address
2C07 (Hexadecimal). Enter the
following key strokes:
SHIFT
0 0
Enters Hex Data Command
2
GHzs
0
7
Address location 2C07 (U13)
hi14
Hex data Rotation Write
Check the outputs of U13 for the waveforms shown in Figure 8-2.
If any output signal is missing or misplaced, check the data lines against
Figure 8-2. If no output is found, look for activity at U13 pin 11. Check for L
INSTl and BA3 to pulse low, while BAO, BAl, and BA2 pulse high. If these
pulses are missing, trace the problem back to A3 Digital Interface.
If the Digital Control section is working, the primary outputs of U13 are easily
controlled by selecting the appropriate front panel function while in the CW
sweep mode
(e.g., selecting
MTR
leveling holds the PM line high, etc.).
Reference Power Level
@ @
The Reference Power Level Leg produces a voltage proportional to the "desired"
power level. This signal is a summation of the absolute power reference, AM,
amplitude markers, ALC compensation, and power sweep signals.
The ALC compensation and power sweep signals are generated on the A5 FM
Driver assembly. If an A5 failure is suspected, refer to troubleshooting
information on the A5 Service Sheet. Unless A5 is suspect, simplify A4
troubleshooting by turning off the line power and removing the
A5
assembly.
Although power sweep will be disabled and the power flatness will be lost, the
ALC loop should still level without the signals provided by the A5 assembly.
DAC U14 establishes the absolute power level. The -lOV REF from the
A6
assembly is scaled to yield from 0 Vdc (-2 dBm displayed) to +lo Vdc (+22
dBm displayed) at TP2. (This breaks down to a voltage step of 0.42 Vdc per 1.0
dB of power over the dynamic range, or 6.25 Vdc at +13
dBm.)
A self-test routine is available to exercise the ALC DAC. Enter:
SHIFT
5
0
8-40
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