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A6 YO DRIVER/A9 REFERENCE RESISTOR. CIRCUIT DESCRIPTION
Input Data Latches
@
FREQ CAL (from the AlIA2 Front Panel) is summed in through U26. (The
BAND
0 line from U22
0
is held high in the 83522A.) This offset corrects
for errors in the Fixed Cavity and YIG Oscillator frequencies.
Frequency Cal Switches/Output Data Buffers
@
NOTE
DIP switches S1 and S2, with their corresponding data bus buffers, are used to
digitally calibrate the low and high end frequencies. The data on these switches
is read by the microprocessor during power-up and I STR PRESET and used
to calculate the settings for the Scale
@and Offset
F
DACs. S1, with pull-up
resistor package
U1, is read through U3 when enable by LEN4. S1 determines
6
the value of the Offset DAC and calibrates the low end frequency. S2, with pull-
up resistor package U2, is read through U4 when enabled by
LENS. This
establishes the Scale DAC values, and calibrates the high end frequency. The
ninth bits from S1 and S2 are read through U7.
Four octal latches store various signals including the digital data for the Scaling
and Offset
@
DACs, and the control signals for the Sweep
ontrolIInterrupt Logic circuit
@.
Each latch is clocked by a separate line from
the Address Decoder to store the byte of data appearing on the Data Bus.
All reference designators refer to the A6 assembly unless
otherwise noted.
LO FREQ FM sums low frequency components of external FM signals
onto the drive voltage when crossover coupling of the FM signal is selected.
(Configuration switch
A3S1 provides this adjustment. Refer to the A3
Service Sheet for further details.) Due to the response time limitations of
the YIG Oscillator's main coil, only frequencies below 700 Hz are passed
from the
A5
FM Driver assembly to the A6 YO assembly.
GENERAL
U8 stores the 8 least significant bits (SO through S7) for the Scaling DAC (U9).
The remaining four bits (S8 through S11) come from half of U13. Similarly, the
least significant bits (00 through 07) for the Offset DAC come from
U18, with
the remaining four (08 through 01 1) coming from the other half of U13. The
8350A microprocessor multiplexes the two numbers so that they can be loaded
in three bytes.
The A6 YO Driver assembly converts the tuning voltage from the
8350A
mainframe into a drive current. The A9 Ref Resistor assembly provides the
current driver to control the frequency of the YIG Oscillator (YO). (The A6
assembly also initiates band-switch sequence in multi-band plug-ins.)
-lOV REF and R25
'ZRO' adjust for gain and offset inaccuracies between
U11
@
and summing amplifier U16.
S1 and S2 switch positions encode binary numbers to set up the Offset and
Scaling DACs. Refer to the Frequency Accuracy adjustment procedure in
Section V for instructions. Figure 8-51 illustrates the switch configurations.
Multiplying Digital-to-Analog Converters (DACs) scale and offset the buffered
tuning voltage to the frequency end-points of the plug-in. A summing amplifier
adds delay compensation, low frequency external FM, and the FREQ CAL
offset from the front panel. The resultant waveform at TP14 is then converted to
a current-drive for the
YO'S Main Coil. Sweep control circuitry interrupts the
microprocessor at the end of each sweep. (Band-switch circuitry is disabled in
the 83522A.)
-1
0V Reference
@
U22 is a control latch which stores commands from the 8350A for the control
lines used on the A6 YO Driver assembly. (Several of these signals are
associated with band-switching circuitry used in multi-band plug-ins and
therefore are not used in this application.) The command byte is latched into
U22 when LEN3 pulses low. Refer to the Summing Amplifier, YO Coil Current
Source, and Sweep
ControlIInterrupt Logic sections for detailed descriptions of
these control lines.
U23 contains a low-noise
6.95V zener diode to provide a stable voltage reference
for the rest of the plug-in. The package includes an internal heater to control its
temperature and improve its stability. R19 and C7 filter the reference voltage to
the non-inverting terminal of differential amplifier U20.
R21, '-lo', adjusts the
overall gain for exactly
-1OV at TP3. C8 limits the high-frequency gain of the
system to reduce noise. R24 provides the bias current for the
zener diode from
the -lOV REF output. R23, with filtering capacitor C9, increases the current
drive capability of the
-10V REF.
The microprocessor reads U7 outputs each time it receives a retrace initiated
interrupt to determine what action is required. LUNLVL, from the A4 ALC
assembly, is read through U7. When the
8350A is under HP-IB control, the
microprocessor alerts the controller to unleveled power conditions.
Tuning Voltage Buffer Amplifier
@
Supply Filtering
@
U10 receives the tuning voltage from the 8350A mainframe and buffers it for use
on the rest of the board. The circuit is arranged as a differential amplifier, with
the tuning signal appearing at the inverting input and the cable shield at the
non-inverting terminal. This provides good common mode rejection to
eliminate noise picked up on the cable. The waveform at TP4 is an inverted
ramp, ranging from
0 to -lOV for sweeping the full frequency range of the plug-
in. See Figure 8-50.
LRFBRQ is not used in the
83522A.
Power supply circuitry provides eight different voltages for the A6 YO Driver
and other assemblies. U27 provides a regulated
+15V supply for the DACs. The
other supplies use capacitive or LC filtering to reduce supply noise.
Sweep Control/lnterrupt Logic
@
+20V Tracking Amplifier
@
YO Coil Current Source
@
YO Coil Current Driver A9
@
Inverting amplifier U11 monitors the +20V line (TP13115) used to supply
current to the YIG Oscillator. If the
+20V supply becomes loaded down or
drifts, the YO Main Coil current and, consequently, the frequency will try to
change. However,
Ul1 senses any drift in the +20V FREQ REF line, and
provides a correction signal so that the resultant YO DRIVE Voltage
(TP14) is
compensated for the drift.
NOTE
Most of the signals discussed in this section are illustrated in
Figure
8-50.
Scaled Voltage Tune DAC
@
Offset
DAC
@
The YIG Coil Current Driver works with Reference Resistor A9RI and YO Coil
Driver
A9Q1 to drive a current proportional to the drive voltage through the
YIG's main tuning coil.
U9 is a 12-bit multiplying DAC, which scales the tuning voltage according to the
binary pattern loaded at its inputs. Inverting amplifier U15 and emitter-follower
Q3 are included in the feedback path to provide the current gain needed to drive
later stages. CRI prevents transients from damaging the DAC during turn-on.
C1, along with the DAC's internal feedback resistor, determine the bandwidth of
the circuit. The waveform at
TPl is a scaled ramp, with a maximum range of 0 to
+10Vdc. See Figure 8-50.
Band-switch circuitry is disabled in the
83522A. The L BSE line from U22 is
held high by microprocessor control, thereby grounding the input to
comparator U5. This effectively disables U5,
U21A, and U17A.
Summing Amplifier
@
U24, Q1, Q2, and A9Q1 comprise a voltage-to-current converter and current
driver for the
YO'S main coil. The non-inverting input of U24 receives the YO
DRIVE Voltage signal. The inverting input of U24 monitors the voltage drop
across reference resistor
A9R1, which is directly proportional to the coil current.
If the drive current is not
tracking the drive voltage, U24 will produce an error
voltage to correct the difference. Emitter-follower
Q1 and common-emitter-stage
Q2 provide the current gain needed to drive
A9Q1. Q1 and Q2 emitter currents
are also drawn through
A9R1, and therefore, sensed by U24. VR1 and CR6
protect the current drive transistors by limiting voltage spikes due to sudden
changes in the coil current. R42 helps to dampen ringing caused by the parasitic
capacitance and the inductance of the YO coil.
U16 provides the summing point for the scaled tuning and offset voltages, and
provides a drive voltage (YO DRIVE
V)
for the Current Driver. Several
correction signals are summed at this junction:
In the
835224 the SS HOLD line is also deactivated by microprocessor control,
disabling
U12A and U12B. However, L SSRQ (Low=Stop Sweep Request) and
L BPRQ
(Low=Blanking Pulse Request) are wire-ored signals and may appear
active at the output, via several other sources.
U19 is a 12-bit multiplying DAC which scales a stable -lOV REF voltage
according to the binary pattern loaded at its inputs. Inverting amplifier U14
works with the
DAC's internal feedback resistor to provide a programmable
offset voltage between
0 and +10Vdc at TP2. See Figure 8-50. CR2 protects the
DAC from turn-on transients.
C11 and the DAC's internal feedback resistor
determine the bandwidth of the circuit.
SC V TUNE provides the scaled ramp portion of the YO DRIVE Voltage.
Rll,
'G',
fine-tunes the range of the scaling DAC
@I.
End of Sweep Interrupt circuitry interrupts the microprocessor at the beginning
and end of each sweep. Each time LRTS
(LovRetrace Strobe) changes from
high to low, or low to high,
U21C pulses high. (Pin 9 of U21C is prevented from
tracking pin 10 by C16. Consequently, the output of EXOR U21C will-pulse high
everytime LRTS changes states.) Each pulse from
U21C clocks flip-flop U17B.
The noninverting output of U17B pulls LSIRQ low and requests microprocessor
attention. LRTS is read through U7 to determine whether the forward sweep is
beginning
(LRTS=High) or ending (LRTS=Low). U17B is then reset by a
control line from U22 and the microprocessor services the interrupt.
OFFSET adjusts the YO DRIVE Voltage so that the YO Coil is driven
between the proper end points, as determined by the front panel controls.
R30,
'OFS', fine-tunes the range of the Offset DAC
@.
When 8350A CW and 83522A CW FILTER are selected, LCW goes low,
energizing relay
K1. C14 filters out noise in the MG coil current, reducing the
residual FM noise in the CW mode.
SUPPLY VOLTAGE CORRECTION provides a compensation signal,
from the
+20V Tracking Amplifier, to offset changes in the reference
supply.
SCVTUNE and OFFSET DACs function together to determine the frequency of
the YIG oscillator. The Offset DAC determines the start frequency while the
Scaling DAC sets the gain of U16 so that SCVTUNE determines the high end
frequency. For full-band sweeps, the entire
0 to -10 Volt VTUNE is scaled and
offset to sweep the YO from 3.81 to 6.2
GHz. The YO output is ten heterodyned
with 3.8
GHz from the Fixed Cavity Oscillator for a full-band range of 0.01 to
2.4
GHz.
CR7, CR3, CR4, and their associated factory-select resistors provide a three
break-point compensation network to correct for non-linearities in the YO
characteristics.
DLY COMP, from the A7 Marker
assembly, is added to correct for lags in
the response time of the
YIG Oscillator.
T~IS
compensation is derived From
SC V TUNE
0.
LRFBRQ is not used in the 83522A. It is activated only during bandswitching in
multi-band plug-ins.
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