System Architecture
There are four main components in the Series
500
processor: the Central Processing Unit (CPU) chip, a
128
Kbit Random Access Memory (RAM) chip, a
256
Kbit
Dynamic RAM (DRAM) chip,
and
an
va Processor (VOP)
chip. These four components communicate via a common
Memory-Processor Bus
(MPB)
and
are the result of
an
advanced photolithography process that can achieve 1.5
micron devices with 1 micron spacings. This
NMOS
process was designed specifically to produce
the
high
performance integrated circuits for the Series
500.
The chip set has self-test logic which automatically
tests
99%
of its devices at power-up.
The
CPU, va Processor
and
RAM Boards are installed
in a card cage called the Memory/Processor Module
(MlPM). The cards are interconnected within
the
Module
by a
36
Mbyte/sec. Memory Processor Bus.
Central Processor Unit
The Series
500
CPU features
the
following:
• A 32-bit, single-chip microprocessor comprised of
450,000 transistors based
on
a stack architecture.
• Three floating point
math
chips to provide superior
performance.
• A direct address range of
500
Mbytes.
•
An
instruction set consisting of
230
operation codes
implemented in a 9 K x 38-bit
ROM control store. The
set provides operations for stack manipulation,
code/data segmentation, shared code in memory
and
va processing.
•
An
18
MHz clock rate
and
a
55
nsec. micro-instruction
cycle time.
• In conjunction with the memory controllers, a scheme
of overlapped memory cycles ("
p
ipelining")
is
implemented in the hardware. The result is a memory
cycle time of
110
nsec.
• Series
500
typical execution times:
Load register from
memory.
. . . .
..
550
nanoseconds
64
bit floating point multiply. . . .
..
1.28 microseconds
32
bit integer multiply. . . . . . . . . .
..
2.92 microseconds
64
bit floating point
add
...........
1.17 microseconds
The unique architecture of the
HP
9000
Series
500
family allows multiple processors to work
simultaneously - each sharing the workload by taking
on
the
next available task. You can
add
up
to two
additional
CPUs to the standard Series
SOO
for a total of
three.
Adding
these CPUs is simply a matter of plugging
in another
CPU Finstrate board (done
by
an
HP
Customer Engineer). It does
not
require
any
operating
system or software changes.
And
you can tune your task
distribution to take full advantage of multiple
CPUs.
2
Memory
The Series
500
Random Access Memory offers the
following set of features:
• Each RAM Board has a
Iv1emory
Controller (MC) chip
that interfaces the RAM chips to the Memory Processor
Bus
and
performs error detection/correction.
• Each memory address contains
32
bits for data
and
7
bits to store a Hamming code which gives each
Memory Controller the ability to locally detect
and
correct all single-bit errors
and
detect all double-bit
errors
and
most multi-bit errors.
• The Series
500
memory utilizes overlapped memory
cycles. With current technology, all models of
the
Series
500
can have
up
to
10
Mbytes of RAM.
During power-up of
the Series 500,
the
system tests
all of its memory by reading
and
writing various data
patterns into each memory location. During this process,
if
any double-bit errors occur or if too
many
single-bit
errors are detected, a block of memory containing the
defective locations
is
mapped
out
by the Memory
Controller with
no
loss of system integrity.
In addition to its power-up memory test, the Series
500
will correct
any
single-bit errors that occur
during
subsequent memory accesses. Double-bit
or
multi-bit
errors are also detected.
I/O Processors
The va Processor
(VOP)
is
a microprogram-controlled
interface between the Series
500' s Memory Processor Bus
and
8 va interface channels. The VOP can handle direct
CPU
va,
generate CPU interrupts
and
conduct
simultaneous,
independent
Direct Memory Access
transactions
on
all 8 va channels.
The modular design of the
vap
permits multiple
vaps
to reside
on
the Merllory Processor Bus
and
function independently. To utilize the additional va
channels of a second or third VOP,
an
HP
97098A
va
Expander
must
be cabled to each VOP.
Features
• Each
vap
supports 8 channels of
va
with Direct
Memory Access capability
on
every channel.
• Up to three
vaps
and
their associated 97098A
va
Expanders are supported
on
Models 520,
530
and
540;
up
to two with the Model
550.
• Nominal
vap
bandwidth
=
900
Kbytes/sec.
(multi-plexed across several channels).
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