Theory
of
Operation 2-31
The power-up sequence begins with self-test execution by
all
processor stack chips. Then the CPU
microcode instructs the lOP to read
R3
of SC7. If bit
14
is
set
in
this register,
it
identifies the
presence of a loader.
If bit
14
is
not set, R3 of
SC6
is
read.
All
select codes are checked
in
descending order until a loader
is
identified as available by bit
14
set.
When the loader
is
found, an
84
hex
is
sent to R 1 of the loader's select code to reset the address
counter to FFFF hex
(0
hex to the chip). This enables direct memory access
(DMA)
and
the self-test
bit.
Through
DMA,
2048
bytes of the loader are input from R4 with the
final
byte from R6. The
ROM
address
is
automatically decremented as the data
is
input. The initial
2K
bytes of loader code
enables the operating system to load the entire 8K loader.
The loader contains code which enables the operating system to be loaded
in
from the system disc.
Several loader modules are contained
in
the loader
ROM.
These include a kernel module, output
modules (for example, ASllterminal), input modules (for example,
HP-IB/CS80),
and
a test mod-
ule. The test module
is
described
and
flowcharted
in
Chapter
3.
If
the Processor Stack contains 1 Megabyte
RAM
boards, Boot Loader
ROM
Rev. B (09020-
80001)
must
be
used,
and
UNIX
4.0 or basic 2.0 software must
be
used.
Boot Loader
ROM Rev
A.
(09020-80000) can
be
used with
UNIX
4.0 or Basic 2.0 (or any previous
software versions) as long as the stack
DOES
NOT
contain a 1 Megabyte
RAM
board.
Boot Loader
ROM Rev. B (09020-80001) can
be
used with any
RAM
configuration
but
MUST use
UNIX
4.0
or Basic 2.0 software.
(Any
earlier versions of software cannot
be
used with this boot
loader. )
Service Panel Interface
Register 10 of
SC7
is
reserved for communication between the service processor
and
the main
system software. The service processor has the ability to read data from the
lOP
and
to write data to
the
lOP via RIO. Refer to Service Processor
Code
description
in
Chapter 3 for details.
Power-Fail Warning
When the power supply assembly detects an impending power failure, a power
fail
Warning (PFW)
is
issued. This causes a response to an
110
poll on
SC7
and
bit 1 to
be
set
in
R2.
The time from
when the warning
is
issued until power shuts down could
be
as little as 1 msec. If power
is
restored,
PFW goes away
and
bit 1
in
R2
is
automatically cleared by the power supply assembly.
High Temperature Warning
When the fans switch to the highest speed because of high ambient temperature or heavy load
on
the power supply, a high temperature warning
is
issued to the system by setting bit 2 of R2
and
responding to the next
110
poll. Once the bit
is
read
it
should
be
cleared by setting bit 1 of R1,
because the signal
is
edge triggered and can come and go. The warning indicates that the power
might
be
shut off at any time to prevent damage to the hardware.
Self-Test
Self-tests can be initiated
in
three ways:
1)
Turn power
on
to automatically perform self-tests; 2)
Set
the enable self-test bit (bit
2)
on
R1
and
write a 1 to bit 5
in
R1;
3) Push the SELF TEST switch
on
the service panel with the enable self-test bit set.
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