2-16
Theory
of
Operation
The 32-bit memory address word
on
the MPB
is
shown
in
Figure 2-7. Bits 0-2 contain the function
code,
and
bits
30
and
31 are used for half-word
and
byte modes, respectively. Bits
3-29
are the
27
bits that specify the logical memory address. The least significant 12 bits of the incoming address are
not mapped. These point to individual locations within the 4K blocks. Eight of the 12 bits
(MPB bits
22-29) comprise th X address. The remaining four bits
(MPB bits 18-21) comprise bits 4-7 of the Y
address. The
15
most significant bits are gated into the
MC
address mapper.
o
r
...
--------LOGICAL
MEMORY
ADDRESS--------i.~1
(27
BITS)
2 3 17
18
29
30
FUNCTION
15
BITS
12
BITS
HALF
CODE
WORD
I
15
I
4
8
{
MAPPER
CAM
3 I
,
, ,
,
!
~
CHIP
ROW
SELECT Y ADDRESS
X ADDRESS
,
PHYSICAL MEMORY ADDRESS
31
BYTE
o 1 2 3 17 18
31
x = DON'T CARE
LOGICAL
PAGE
NUMBER
MAPPER
CAM
DATA FORMAT
Figure 2-7. 256K Memory Mapping Operation
Bits 3-1 7 of the MPB logical memory address are compared with bits 3-1 7 of each mapper
CAM
register
in
the
MC
address mapper.
If
the compare
is
unsuccessful, nothing happens.
If
a compare
is
successful, bit 0 of the register
is
then checked. If bit 0 (the map
out
bit)
is
set, the addressed
RAM
block
is
considered nonexistent
and
cannot be accessed. This allows defective memory blocks to be
removed from use
and
assures that no logical address
will
be
mapped onto
an
empty block of
memory.
If
an
address compare occurs
and
the mapper
CAM
register
map
out
bit
is
clear, the
MC
produces a
19-bit physical memory address. The address mapper sets
one
of four chip select lines to select
one
of four chip rows. It also outputs three bits which are joined with
MPB
bits 18-21 to form the 7 -bit Y
address.
MPB bits
22-29
are gated
in
as the 8-bit X address. The most significant bit of the Y
address
is
not used. The next two bits select the l-of-4 block number. The lower four bits of the Y
address
and
the eight X address bits select
one
of 4K words
in
the block.
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