IBM 1 Series - Page 53

Poll Mechanism
2-42
GA34-0033
The circuit shown in Figure 2-16 enables the poll mechanism to be kept
independent of ‘data strobe’ and prevents storage-related ‘data strobes’
from activating the ‘service gate return’ for a device unless it has been
selected specifically for service. Note that ’address bus bit 16’ is not used
to determine selection for the interrupt or cycle-steal sequence. Note also
that ‘data strobe’ does not participate in the setting of the service gate
capture trigger. The complement of the service gate capture trigger @
resets the poll capture latch. This ensures that the service gate capture
trigger is fully latched prior to resetting the poll capture latch, which in
turn removes the set condition for the service gate capture trigger. The
service gate capture trigger is reset @ by either the deactivation of ‘service
gate’ or ‘data strobe,’ whichever occurs later in the sequence.
Two arbitrary delays are shown in series with the return tags @ @. The
input to the delay is the envelope of the respective tag. The two envelopes
can be used conveniently by the device to gate data to the interface and to
gate with ‘data strobe.’ The delay should allow for appropriate data and
condition code activation and deactivation on the interface in correct
relationship with the return tag.
The figure also illustrates deselection and degating of return tags with any
of the three synchronous channel-directed resets. Note that Device Reset
(which is a DPC command) is not included in these resets, because its
action is different. This is explained in the discussion of the poll
mechanism, which follows.
The operational sequence for polling has the means designed into it for
eliminating the classical test and set condition and for minimizing the
effects of metastability. Figures 2-17 and 2-18 show a typical poll
mechanism for non-burst cycle-stealing and interrupt polling. A single
device adapter is assumed.
As shown on the left side of Figure 2-17, there are two types of requests:
cycle-steal request @ and interrupt request @. These requests, whose
sources in the device would be latches, are presented to the interface after
suitable gating @ @. In the case of an interrupt request, the level bits
previously loaded by a Prepare command are decoded to present a request
on one of the ‘request in bus’ lines @. The I-bit (interrupt enable) loaded
by the Prepare command is used to gate the request-in bus and the poll
propagate/poll return function.
The active conditions of the ‘poll ID’ bits are detected for cycle-steal and
interrupt, respectively. The ‘-poll ID bit 0’ line is enabled for cycle-steal,
quiescent state, and some reserved functions; therefore, an inactive ‘-poll
ID bit 0’ indicates a poll for an interrupt request. Also, ‘poll ID’ bits 1-4
are compared with the level bits to determine if the requested level of
interrupt matches the level being polled.