IBM 7090 - Page 17

Besides performing a temporary storage function, the registers described also offer
the ability to break the 36-position word into lesser groups. You will see that particu-
lar ly the operation code and the address are extracted from the whole instruction word
and placed in separate registers. You will also see the use of the address field of the
instruction word as a part of the operation code.
Note that the descriptions in this section are elementary and only as complete as is
required for the problem A +B = C, print C. Other registers and switching functions
will be described in later sections.
The calculator entry and calculator exit handle information coming from or going to
the card machines (reader, punch, or printer). There is no storage here, but informa-
tion waits at these points until the data register is ready to receive the information from
calculator entry or the card punch is ready to receive the information from calculator
exit.
The data register is the receiving and distributing point for data passing to and from
the data channel. Data words are received here from input units for forwarding to
storage. Data words also come from storage to this register for forwarding to output
units.
The channel address counter, word counter, and operation register (with the com-
mand location counter) are the operating controls in the data channel. Because the lo-
cation counter is not needed in A+B = C, print C, it has been omitted from Figure 2.3-1.
The channel address counter holds the storage address for the data word being cur-
rently handled in the data channel. As a register, this counter receives a beginning
address from the address field of a command coming into a channel. As each word is
handled, the channel address counter advances one count. Thus, words are stored from
channel input in consecutive ascending locations in storage. Likewise, words withdrawn
from storage for output come from consecutive ascending locations.
The word counter, as a register, receives a word count from a command coming into
a data channel. As 'a counter, it is reduced by one each time a word is handled. The
data channel recognizes zero in the word counter as a signal that the command has been
completely executed.
The operation register receives the prefix portion of a command word coming into a
data channel. This register is decoded to dictate what operation is to be performed.
The memory address register receives, through the multiplexor, the address of a
storage word location to be entered or read out. This address may originate in the
CPU or in the data channel.
The memory data register receives a word either from a storage location, or
(through the multiplexor) from the CPU or the data channel. The latter case is for the
purpose of storing the word at the addressed location; the former is a read-out to the
CPU or data channel from the addressed location.
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