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IBM 7090 - 5.0.00 CPU DATA FLOW AND TIMING; 5.1.00 I CYCLE; 5.2.00 INDIRECT ADDRESSING

IBM 7090
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5.
O.
00
CPU
DATA
FLOW
AND TIMING
5.1.
00 I
CYCLE
I
cycle
operation
is
much
the
same
for
all
instructions.
E
and
L
cycle
operations
vary
depending
on
the
instruction.
I
cycle
operation
is
shown
in
Figure
5.1-1.
The
end
operation
trigger
(END
OP
TGR)
is
turned
on
during
the
last
cycle
of
an
operation
and
for
an
initial
starting
condition.
This
causes
the
I
time
trigger
to
be
turned
on.
Also
with
the
end
operation
trigger
on,
the
address
of
the
instruction
is
sent
to
core
storage.
The
instruction
is
then
taken
from
that
address
in
core
storage
and
sent
to
the
CPU
on
the
storage
bus
(SB).
The
instruction
is
put
into
the
storage
register
(SR)
and
the
operation
code
is
sent
to
the
program
register
(PR).
Note
the
difference
between
instructions
with
a
bit
in
positions
1
and
2 and
those
without
a
bit
in
1
or
2.
Few
instructions
have
a
bit
in
positions
1
or
2.
When
the
instruction
is
decoded
the
computer
will
decide
what
kind
of a
cycle
is
to
be
taken.
Most
instructions
requiring
an
L
cycle
have
operation
codes
0-177
or
from
700
on.
Instructions
with
operation
codes
between
these
limits
usually
require
an
E
cycle.
The
exceptions
to
these
general
Land
E
time
call
rules
are
in
the
MF
systems
pages.
Some
instructions
require
only
one
cycle;
therefore,
the
end
operation
trigger
is
turned
on
during
I
time.
This
forces
"go
to
I
time"
on
Systems
8.00.
12.
1.
"Go
to
I
time"
will
turn
on
the
master
I
time
trigger
and
will
prevent
turning
on of
the
master
E
or
L
time
triggers.
The
program
counter
is
advanced
to
give
the
location
of
the
next
sequential
instruc-
tion
in
core
storage.
The
address
portion
of
the
instruction
is
sent
to
the
address
register.
For
primary
operations
76
it
is
sent
to
the
shift
counter.
The
address
in
the
address
register
is
used
to
locate
a
particular
address
in
storage
if
the
next
cycle
is
an
E
cycle.
Part
of
the
address
is
sent
to
the
shift
counter
on
primary
operations
76.
The
shift
counter
is
used
on
these
operations
along
with
the
program
register
to
instruct
the
system.
5.2.00
INDIRECT
ADDRESSING
Indirect
addressing
is
a
programming
device
which
permits
changing
an
instruction
address.
Bits
in
positions
12
and
13
of
an
instruction
are
signals
for
indirect
address-
ing.
This
causes
an
E
cycle,
during
which
the
word
located
at
the
original
instruction
address
is
read
out
of
storage
and
its
address
portion
is
substituted
for
the
instruction
address.
The
instruction
then
operates
on
the
new
address.
Only
indexable
instruc-
tions
may
be
indirectly
addressed.
The
only
change
in
operation
of
an
instruction
caused
by
indirect
addressing
is
the
insertion
of
an
E
cycle.
As
with
direct
address
instructions,
indexing
is
automatic.
45

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