IBM 7090 - Page 40

Memory Data CPU
Channel
Channel
CPU
Register
Out Storage Register Stg Bus Sw's
Address Sw's Address Register
Sw's
0- -71
S
1- -35
S 1-
-35
3-
-17
3-
-17
I
~
r
,
,
Multiplexor
Multiplexor Multiplexor
Storage Bus
Storage Bus Address Switches
OR'ing
S
1-
-20 I 21-35
S, 1-
-35 3-
-17
r--
-
-
It
CPU
Channel
Memory Data
Memory
Channel Location
Storage
Bus
Input Switches
Register
in
Address Register
Counter Sw's
Sw's
S 1- -35
S
1-
-35
0- -71 3- -17
3-
-17
FIGURE 4.0-1. FLOW TO AND FROM THE MULTIPLEXOR
39