IBM 7090 - Page 72

add. If it were a normalizing instruction, a check would be made to see if a 1 were in
AC position nine. If AC(9) does contain a 1, the operation would be complete; if not,
the AC would shift left until a one did appear in position nine. Shifting increases the
number, so to keep it the same, the characteristic is reduced by the number of left
shifts taken. Floating-point subtraction works the same except that the fractions are
subtracted.
Floating-point divide is accomplished by dividing the fraction of the dividend by the
fraction of the divisor and subtracting the characteristics. During the subtraction of
the characteristics, the 2008 that is added to all exponents is lost. Therefore, before
the answer is final, 2008 must be added to the quotient characteristic.
Floating multiply is accomplished by multiplying the fraction in the SR by the fraction
in the MQ. The exponents in multiply are added, so in a floating multiply, the computer
adds the characteristics. Because 2008 had been added to each exponent originally,
the characteristic is increased by 4008 after the addition. Before the answer is final,
2008 must be subtracted from the characteristic. The most significant part of the prod-
uct is in the AC and the least significant part in the MQ.
Sign control is as follows:
Multiplication and Division
Addition
Subtraction
Floating-Point Tally Counter
Signs of factors alike; answer plus
Signs of factors unlike; answer minus
Answer always has sign of the largest factor
After sign of SR is inverted, answer always has
sign of the largest factor
The floating-point add, multiply, and divide type instructions require an I, an E,
and several L cycles. Execution of the instruction is accomplished during the L cycles.
To differentiate between the different types of L cycles, there is a tally counter. This
is a five stage counter whose output is added with L time to direct the various phases
in the execution of the instruction. When the required operations are complete for
first step L time, the tally counter is stepped to produce second step L time. This
causes the computer to go into the next phase in the execution of the instruction. The
operation continues to the next step, and so on. All five steps of the tally counter are
not used for every instruction; each instruction uses as many as it requires.
Floating Add FAD +0300 (Min I, E, 4L) Figure 5.3-23
(Max I, E, 13L)
This instruction adds, algebraically, the floating-point number stored at the location
indicated by the address and the floating-point number contained in the accumulator.
The most Significant portion of the result appears as a normalized floating-point number
in the accumulator. The least significant portion of the result appears in the MQ as a
floating-point number with a characteristic 2710 less than the characteristic of the
number in the accumulator. The signs of the AC and MQ are set to the sign of the
larger factor. If both the resulting MQ and AC fractions are zero, the registers will
be reset to contain normal zeros with the signs corresponding to the original factor
having the smaller characteristic. If the characteristics were equal, the resulting
signs will correspond to the original AC sign.
The result in the AC is always normalized, whether the original factors were normal
or not. No attempt is made to normalize the MQ.
First Step L Time. As first step L time is entered, one of the floating-point words
to be added is in the AC and the other is in the SR. The objectives of 1st step L time
are to:
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