IBM PowerPC 750GX

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
List of Tables
Page 16 of 377
750gx_umLOT.fm.(1.2)
March 27, 2006
Table 2-34. SPR Encodings for 750GX-Defined Registers (mfspr) ........................................................112
Table 2-35. Memory Synchronization Instructions—UISA .......................................................................113
Table 2-36. Move-from Time Base Instruction .........................................................................................114
Table 2-37. Memory Synchronization Instructions—VEA ........................................................................115
Table 2-38. User-Level Cache Instructions .............................................................................................116
Table 2-39. External Control Instructions ................................................................................................117
Table 2-40. System Linkage Instructions—OEA .....................................................................................118
Table 2-41. Move-to/Move-from Machine State Register Instructions .....................................................118
Table 2-42. Move-to/Move-from Special-Purpose Register Instructions (OEA) ......................................118
Table 2-43. Supervisor-Level Cache-Management Instruction ...............................................................119
Table 2-44. Segment Register Manipulation Instructions ........................................................................119
Table 2-45. Translation Lookaside Buffer Management Instruction ........................................................120
Table 3-1. MEI State Definitions ............................................................................................................127
Table 3-2. PLRU Bit Update Rules ........................................................................................................138
Table 3-3. PLRU Replacement Block Selection ....................................................................................138
Table 3-4. Bus Operations Caused by Cache-Control Instructions (WIM = 001) ..................................141
Table 3-5. Response to Snooped Bus Transactions .............................................................................143
Table 3-6. Address/Transfer Attribute Summary ...................................................................................146
Table 3-7. MEI State Transitions ...........................................................................................................147
Table 4-1. PowerPC 750GX Microprocessor Exception Classifications ................................................152
Table 4-2. Exceptions and Conditions ...................................................................................................152
Table 4-3. Exception Priorities ...............................................................................................................155
Table 4-4. IEEE Floating-Point Exception Mode Bits ............................................................................160
Table 4-5. MSR Setting Due to Exception .............................................................................................162
Table 4-6. System Reset Exception–Register Settings .........................................................................163
Table 4-7. Settings Caused by Hard Reset ...........................................................................................166
Table 4-8. HID0 Machine-Check Enable Bits ........................................................................................167
Table 4-9. Machine-Check Exception—Register Settings .....................................................................168
Table 4-10. Performance-Monitor Interrupt Exception—Register Settings ..............................................172
Table 4-11. Instruction Address Breakpoint Exception—Register Settings .............................................173
Table 4-12. System Management Interrupt Exception—Register Settings .............................................174
Table 4-13. Thermal-Management Interrupt Exception—Register Settings ............................................174
Table 4-14. Front-End Exception Handling Summary .............................................................................176
Table 5-1. MMU Feature Summary .......................................................................................................180
Table 5-2. Access Protection Options for Pages ...................................................................................188
Table 5-3. Translation Exception Conditions .........................................................................................192
Table 5-4. Other MMU Exception Conditions for the 750GX Processor ................................................193
Table 5-5. 750GX Microprocessor Instruction Summary—Control MMUs ............................................194
Table 5-6. 750GX Microprocessor MMU Registers ...............................................................................195