User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Power and Thermal Management
Page 348 of 377
gx_10.fm.(1.2)
March 27, 2006
The bit field settings of the ICTC SPR are shown in Table 10-4 on page 348.
Table 10-4. ICTC Bit Field Settings
Bits Name Description
0-22 Reserved
Bits reserved for future use. The system software should always write zeros to these bits when writing to
the THRM SPRs.
23–30 FI
Instruction forwarding interval expressed in processor clocks.
0x00 0 clock cycle
0x01 1 clock cycle
.
.
0xFF 255 clock cycles
31 E
Cache throttling enable
0 Disable instruction-cache throttling.
1 Enable instruction-cache throttling.
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