User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_07.fm.(1.2)
March 27, 2006
Signal Descriptions
Page 263 of 377
7.2.5.2 Address Retry (ARTRY)
The address retry (ARTRY
) signal is both an input and output signal on the 750GX.
Address Retry (ARTRY
)—Output
State Asserted The 750GX as snooper indicates that the 750GX requires the snooped trans-
action to be rerun. The 750GX might require a snooped transaction to rerun
to perform a snoop copyback first, because it is currently performing a cache
reload for that line (pipeline collision on bus), or because it was unable to
service the snooped address at that time.
Negated/
High
Impedance
Indicates that the 750GX does not need the snooped address tenure to be
retried.
Timing Assertion Driven and asserted the second cycle following the assertion of TS
if a retry
is required. Remains asserted until the cycle following the assertion of
AACK
.
Negation Occurs the second bus cycle after the assertion of AACK
. Since this signal
might be simultaneously driven by multiple devices, it negates in a unique
fashion. First the buffer goes to high impedance for a minimum of one-half
processor cycle (dependent on the clock mode), and then it is driven negated
for one-half bus cycle before returning to high impedance. This special
method of negation can be disabled by setting precharge disable in
HID0[PAR].
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