User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_02.fm.(1.2)
March 27, 2006
Programming Model
Page 77 of 377
2.1.3 Instruction Cache Throttling Control Register (ICTC)
Reducing the rate of instruction fetching can control junction temperature without the complexity and over-
head of dynamic clock control. System software can control instruction forwarding by writing a nonzero value
to the supervisor-level ICTC register. The overall junction temperature reduction comes from the dynamic
power management of each functional unit when the 750GX is idle in between instruction fetches. PLL
(phase-locked loop) and DLL (delay-locked loop) configurations are unchanged.
Instruction-cache throttling is enabled by setting ICTC[E] and writing the instruction forwarding interval into
ICTC[FI]. Enabling, disabling, and changing the instruction forwarding interval immediately affect instruction
forwarding.
The ICTC register can be accessed with the mtspr and mfspr instructions using SPR 1019.
Reserved FI E
012345678910111213141516171819202122232425262728293031
Bits Field Name Description
0:22 Reserved
Reserved for future use. The system software should always write zeros to these bits
when writing to the THRM SPRs.
23:30 FI
Instruction forwarding interval expressed in processor clocks.
0x00 0 clock cycles
0x01 1 clock cycle
.
.
0xFF 255 clock cycles
31 E
Cache throttling enable
0 Disable instruction-cache throttling.
1 Enable instruction-cache throttling.
To Next Page
Loading...
Need help?
General
