User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Instruction Timing
Page 236 of 377
gx_06.fm.(1.2)
March 27, 2006
6.5.2 Effect of TLB Miss
If a page-address translation is not in a translation lookaside buffer (TLB), the 750GX hardware searches the
page tables and updates the TLB when a translation is found. Table 6-3 shows the estimated latency for the
hardware TLB load for different cache configurations and conditions.
The page table entry (PTE) table search assumes a hit in the first entry of the primary page-table-entry group
(PTEG).
6.6 Instruction Scheduling Guidelines
The performance of the 750GX can be improved by avoiding resource conflicts and scheduling instructions to
take fullest advantage of the parallel execution units. Instruction scheduling on the 750GX can be improved
by observing the following guidelines:
• To reduce mispredictions, separate the instruction that sets CR bits from the branch instruction that eval-
uates them. Because there can be no more than 12 instructions in the processor (with the instruction that
sets CR in CQ0 and the dependent branch instruction in IQ5), there is no advantage to having more than
10 instructions between them.
• Likewise, when branching to a location specified by the CTR or LR, separate the mtspr instruction that
initializes the CTR or LR from the dependent branch instruction. This ensures the register values are
available sooner to the branch instruction.
• Schedule instructions so that two can be dispatched at a time.
• Schedule instructions to minimize stalls due to execution units being busy.
• Avoid scheduling high-latency instructions close together. Interspersing single-cycle latency integer
instructions between longer-latency instructions minimizes the effect that instructions such as integer and
floating-point divide and multiply can have on throughput.
• Avoid using serializing instructions.
• Schedule instructions to avoid dispatch stalls.
– Six instructions can be tracked in the completion queue. Therefore, only six instructions can be in the
execute stages at any one time.
– There are six GPR Rename Registers. Therefore, only six GPRs can be specified as destination
operands at any time. If no Rename Registers are available, instructions cannot enter the execute
stage and remain in the reservation station or instruction queue until they become available.
Note: Load with update address instructions use two Rename Registers.
– Similarly, there are six FPR Rename Registers, so only six FPR destination operands can be in the
execute and complete stages at any time.
Table 6-3. TLB Miss Latencies
L1 Condition
(Instruction and Data)
L2 Condition
Processor/System Bus
Clock Ratio
Estimated Latency
(Cycles)
100% cache hit — — 7
100% cache miss 100% cache hit — 13
100% cache miss 100% cache miss 2.5:1 (6:3:3:3 memory) 62
100% cache miss 100% cache miss 4:1 (5:2:2:2 memory) 77
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