User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Bus Interface Operation
Page 312 of 377
gx_08.fm.(1.2)
March 27, 2006
Figure 8-19 shows three ways to delay single-beat reads using data-delay controls:
• The TA
signal can remain negated to insert wait states in clock cycles 3 and 4.
• For the second access, DBG
could have been asserted in clock cycle 6.
• In the third access, DRTRY
is asserted in clock cycle 11 to flush the previous data.
Note: All bidirectional signals are tristated between bus tenures. The pipelining shown in Figure 8-19 can
occur if the second access is not another load (for example, an instruction fetch).
Figure 8-19. Single-Beat Reads Showing Data-Delay Controls
BR
BG
ABB
TS
A[0–31]
TT[0–4]
TBST
GBL
AACK
ARTRY
DBG
DBB
D[0–63]
TA
DRTRY
TEA
CPU A CPU A CPU A
Read Read Read
In In Bad
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14
In
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