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IBM PowerP
C 750GX
and 750GL RISC M
icroprocessor
List of Tables
Page 18 o
f 377
750gx_umLOT.fm.(1.2)
March 27, 2006
Table
11-7.
HID2 Check
stop Control
Bits
..................
.............
...................
.............
...................
.............
.
362
Table
11-8.
L2CR Che
ckstop Control
Bits
.................
.............
...................
.............
...................
.............
.
362
17
19
Table of Contents
Default Chapter
3
Default Chapter
3
Table of Contents
3
List of Figures
13
List of Tables
15
About this Manual
19
Who Should Read this Manual
19
Related Publications
19
Conventions Used in this Manual
20
Using this Manual with the Programming Environments Manual
22
1 Powerpc 750GX Overview
23
750GX Microprocessor Overview
23
Figure 1-1. 750GX Microprocessor Block Diagram
23
750GX Microprocessor Features
25
Instruction Flow
29
Branch Processing Unit (BPU)
29
Instruction Queue and Dispatch Unit
29
Completion Unit
30
Floating-Point Unit (FPU)
31
Independent Execution Units
31
Integer Units (Ius)
31
Load/Store Unit (LSU)
32
Memory Management Units (Mmus)
32
System Register Unit (SRU)
32
On-Chip Level 1 Instruction and Data Caches
33
Figure 1-2. L1 Cache Organization
34
On-Chip Level 2 Cache Implementation
35
System Interface/Bus Interface Unit (BIU)
35
Figure 1-3. System Interface
37
Signals
37
Signal Configuration
38
Figure 1-4. 750GX Microprocessor Signal Groups
39
Clocking
40
750GX Microprocessor Implementation
40
Powerpc Registers and Programming Model
42
Table 1-1. Architecture-Defined Registers (Excluding Sprs)
42
Table 1-2. Architecture-Defined Sprs Implemented
43
Table 1-3. Implementation-Specific Registers
44
Instruction Set
45
Powerpc Instruction Set
45
750GX Microprocessor Instruction Set
47
On-Chip Cache Implementation
47
750GX Microprocessor Cache Implementation
47
Powerpc Cache Model
47
Exception Model
48
Powerpc Exception Model
48
750GX Microprocessor Exception Implementation
49
Table 1-4. 750GX Microprocessor Exception Classifications
49
Table 1-5. Exceptions and Conditions
50
Memory Management
51
Powerpc Memory-Management Model
51
750GX Microprocessor Memory-Management Implementation
52
Instruction Timing
52
Figure 1-5. Pipeline Diagram
53
Power Management
54
Thermal Management
55
Performance Monitor
56
2 Programming Model
57
Powerpc 750GX Processor Register Set
57
Register Set
57
Figure 2-1. Powerpc 750GX Microprocessor Programming Model-Registers
58
Table 2-1. Additional MSR Bits
60
Table 2-2. Additional SRR1 Bits
62
Powerpc 750GX-Specific Registers
64
Instruction Address Breakpoint Register (IABR)
64
Hardware-Implementation-Dependent Register 0 (HID0)
65
Hardware-Implementation-Dependent Register 1 (HID1)
70
Hardware-Implementation-Dependent Register 2 (HID2)
71
Performance-Monitor Registers
72
Instruction Cache Throttling Control Register (ICTC)
77
Thermal-Management Registers (Thrmn)
78
Thermal-Management Registers 1-2 (THRM1-THRM2)
78
Table 2-3. Valid THRM1/THRM2 Bit Settings
79
Thermal-Management Register 3 (THRM3)
79
Thermal-Management Register 4 (THRM4)
80
L2 Cache Control Register (L2CR)
81
Operand Conventions
82
Data Organization in Memory and Data Transfers
82
Alignment and Misaligned Accesses
82
Table 2-4. Memory Operands
82
Floating-Point Operand and Execution Models-UISA
83
Denormalized Number Support
83
Non-IEEE Mode (Nondenormalized Mode)
83
Floating-Point Storage Access Alignment
84
Optional Floating-Point Graphics Instructions
84
Table 2-5. Floating-Point Operand Data-Type Behavior
84
Time-Critical Floating-Point Operation
84
Table 2-6. Floating-Point Result Data-Type Behavior
85
Instruction Set Summary
86
Classes of Instructions
87
Defined Instruction Class
87
Definition of Boundedly Undefined
87
Illegal Instruction Class
88
Reserved Instruction Class
89
Addressing Modes
89
Memory Addressing
89
Memory Operands
89
Effective Address Calculation
90
Synchronization
90
Instruction Set Overview
91
Powerpc UISA Instructions
92
Integer Instructions
92
Table 2-7. Integer Arithmetic Instructions
92
Table 2-8. Integer Compare Instructions
93
Table 2-9. Integer Logical Instructions
94
Floating-Point Instructions
95
Table 2-10. Integer Rotate Instructions
95
Table 2-11. Integer Shift Instructions
95
Table 2-12. Floating-Point Arithmetic Instructions
96
Table 2-13. Floating-Point Multiply/Add Instructions
96
Table 2-14. Floating-Point Rounding and Conversion Instructions
97
Table 2-15. Floating-Point Compare Instructions
97
Table 2-16. Floating-Point Status and Control Register Instructions
97
Load-And-Store Instructions
98
Table 2-17. Floating-Point Move Instructions
98
Table 2-18. Integer Load Instructions
99
Table 2-19. Integer Store Instructions
101
Table 2-20. Integer Load-And-Store with Byte-Reverse Instructions
102
Table 2-21. Integer Load-And-Store Multiple Instructions
102
Table 2-22. Integer Load-And-Store String Instructions
103
Table 2-23. Floating-Point Load Instructions
104
Table 2-24. Floating-Point Store Instructions
105
Table 2-25. Store Floating-Point Single Behavior
105
Table 2-26. Store Floating-Point Double Behavior
105
Branch and Flow-Control Instructions
106
Table 2-27. Branch Instructions
107
Table 2-28. Condition Register Logical Instructions
107
Processor Control Instructions-UISA
108
System Linkage Instruction-UISA
108
Table 2-29. Trap Instructions
108
Table 2-30. System Linkage Instruction-UISA
108
Table 2-31. Move-To/Move-From Condition Register Instructions
108
Table 2-32. Move-To/Move-From Special-Purpose Register Instructions (UISA)
109
Table 2-33. Powerpc Encodings
109
Table 2-34. SPR Encodings for 750GX-Defined Registers (Mfspr)
112
Memory Synchronization Instructions-UISA
113
Powerpc VEA Instructions
113
Processor Control Instructions-VEA
113
Table 2-35. Memory Synchronization Instructions-UISA
113
Memory Synchronization Instructions-VEA
114
Table 2-36. Move-From Time Base Instruction
114
Memory Control Instructions-VEA
115
Table 2-37. Memory Synchronization Instructions-VEA
115
Table 2-38. User-Level Cache Instructions
116
Optional External Control Instructions
117
Table 2-39. External Control Instructions
117
Powerpc OEA Instructions
118
Processor Control Instructions-OEA
118
System Linkage Instructions-OEA
118
Table 2-40. System Linkage Instructions-OEA
118
Table 2-41. Move-To/Move-From Machine State Register Instructions
118
Table 2-42. Move-To/Move-From Special-Purpose Register Instructions (OEA)
118
Memory Control Instructions-OEA
119
Table 2-43. Supervisor-Level Cache-Management Instruction
119
Table 2-44. Segment Register Manipulation Instructions
119
Recommended Simplified Mnemonics
120
Table 2-45. Translation Lookaside Buffer Management Instruction
120
3 Instruction-Cache and Data-Cache Operation
121
Figure 3-1. Cache Integration
122
Data-Cache Organization
123
Figure 3-2. Data-Cache Organization
123
Instruction-Cache Organization
124
Memory and Cache Coherency
125
Memory/Cache Access Attributes (WIMG Bits)
125
Figure 3-3. Instruction-Cache Organization
125
MEI Protocol
126
Table 3-1. MEI State Definitions
127
Figure 3-4. MEI Cache-Coherency Protocol-State Diagram (WIM = 001)
128
MEI Hardware Considerations
128
Coherency Precautions in Multiprocessor Systems
129
Coherency Precautions in Single-Processor Systems
129
Atomic Memory References
130
Performed Loads and Stores
130
Powerpc 750GX-Initiated Load/Store Operations
130
Sequential Consistency of Memory Accesses
130
Cache Control
131
Cache-Control Parameters in HID0
131
Data-Cache Flash Invalidation
132
Enabling and Disabling the Data Cache
132
Locking the Data Cache
132
Cache-Control Instructions
133
Enabling and Disabling the Instruction Cache
133
Instruction-Cache Flash Invalidation
133
Locking the Instruction Cache
133
Data Cache Block Touch (Dcbt) and Data Cache Block Touch for Store (Dcbtst)
134
Data Cache Block Zero (Dcbz)
134
Data Cache Block Flush (Dcbf)
135
Data Cache Block Invalidate (Dcbi)
135
Data Cache Block Store (Dcbst)
135
Instruction Cache Block Invalidate (Icbi)
136
Cache Operations
136
Cache-Block-Replacement/Castout Operations
136
Figure 3-5. PLRU Replacement Algorithm
137
Cache Flush Operations
138
Table 3-2. PLRU Bit Update Rules
138
Table 3-3. PLRU Replacement Block Selection
138
Data-Cache Block-Fill Operations
139
Data-Cache Block-Push Operations
139
Instruction-Cache Block-Fill Operations
139
L1 Caches and 60X Bus Transactions
139
Figure 3-6. 750GX Cache Addresses
140
Read Operations and the MEI Protocol
140
Bus Operations Caused by Cache-Control Instructions
141
Table 3-4. Bus Operations Caused by Cache-Control Instructions (WIM = 001)
141
Snooping
142
Snoop Response to 60X Bus Transactions
143
Table 3-5. Response to Snooped Bus Transactions
143
Transfer Attributes
145
Table 3-6. Address/Transfer Attribute Summary
146
MEI State Transactions
147
Table 3-7. MEI State Transitions
147
4 Exceptions
151
Powerpc 750GX Microprocessor Exceptions
152
Table 4-1. Powerpc 750GX Microprocessor Exception Classifications
152
Table 4-2. Exceptions and Conditions
152
Exception Recognition and Priorities
153
Table 4-3. Exception Priorities
155
Exception Processing
156
Machine Status Save/Restore Register 0 (SRR0)
156
Machine Status Save/Restore Register 1 (SRR1)
157
Machine State Register (MSR)
158
Enabling and Disabling Exceptions
160
Steps for Exception Processing
160
Table 4-4. IEEE Floating-Point Exception Mode Bits
160
Setting MSR[RI]
161
Returning from an Exception Handler
161
Process Switching
162
Exception Definitions
162
Table 4-5. MSR Setting Due to Exception
162
System Reset Exception (0X00100)
163
Table 4-6. System Reset Exception-Register Settings
163
Figure 4-1. SRESET Asserted During HRESET
164
Hard Reset
164
Soft Reset
164
Table 4-7. Settings Caused by Hard Reset
166
Machine-Check Exception (0X00200)
167
Table 4-8. HID0 Machine-Check Enable Bits
167
Machine-Check Exception Enabled (MSR[ME] = 1)
168
Table 4-9. Machine-Check Exception-Register Settings
168
Checkstop State (MSR[ME] = 0)
169
DSI Exception (0X00300)
169
External Interrupt Exception (0X00500)
169
ISI Exception (0X00400)
169
Alignment Exception (0X00600)
170
Program Exception (0X00700)
170
Decrementer Exception (0X00900)
171
Floating-Point Assist Exception (0X00E00)
171
Floating-Point Unavailable Exception (0X00800)
171
System Call Exception (0X00C00)
171
Trace Exception (0X00D00)
171
Performance-Monitor Interrupt (0X00F00)
172
Table 4-10. Performance-Monitor Interrupt Exception-Register Settings
172
Instruction Address Breakpoint Exception (0X01300)
173
System Management Interrupt (0X01400)
173
Table 4-11. Instruction Address Breakpoint Exception-Register Settings
173
Table 4-12. System Management Interrupt Exception-Register Settings
174
Table 4-13. Thermal-Management Interrupt Exception-Register Settings
174
Thermal-Management Interrupt Exception (0X01700)
174
Data Address Breakpoint Exception
175
Data Address Breakpoint Register (DABR)
175
Soft Stops
175
Exception Latencies
176
Summary of Front-End Exception Handling
176
Table 4-14. Front-End Exception Handling Summary
176
External Access Instructions
177
Timer Facilities
177
5 Memory Management
179
MMU Overview
179
Table 5-1. MMU Feature Summary
180
Figure 5-1. MMU Conceptual Block Diagram
181
Figure 5-2. Powerpc 750GX Microprocessor IMMU Block Diagram
181
Memory Addressing
181
MMU Organization
181
Figure 5-3. 750GX Microprocessor DMMU Block Diagram
185
Address-Translation Mechanisms
186
Figure 5-4. Address-Translation Types
186
Memory-Protection Facilities
187
Page History Information
188
Table 5-2. Access Protection Options for Pages
188
General Flow of MMU Address Translation
189
Figure 5-5. General Flow of Address Translation (Real-Addressing Mode and Block)
189
Real-Addressing Mode and Block-Address-Translation Selection
189
Figure 5-6. General Flow of Page and Direct-Store Interface Address Translation
190
Page-Address-Translation Selection
190
MMU Exceptions Summary
192
Table 5-3. Translation Exception Conditions
192
Table 5-4. Other MMU Exception Conditions for the 750GX Processor
193
MMU Instructions and Register Summary
194
Table 5-5. 750GX Microprocessor Instruction Summary-Control Mmus
194
Real-Addressing Mode
195
Table 5-6. 750GX Microprocessor MMU Registers
195
Block-Address Translation
196
Memory Segment Model
196
Page History Recording
196
Referenced Bit
197
Table 5-7. Table-Search Operations to Update History Bits-TLB Hit Case
197
Changed Bit
198
Scenarios for Referenced and Changed Bit Recording
198
Table 5-8. Model for Guaranteed R and C Bit Settings
198
Page Memory Protection
199
TLB Description
199
TLB Organization
199
Figure 5-7. Segment Register and DTLB Organization
200
TLB Invalidation
201
Page-Address-Translation Summary
202
Figure 5-8. Page-Address-Translation Flow-TLB Hit
203
Page Table-Search Operation
204
Figure 5-9. Primary Page Table Search
205
Figure 5-10. Secondary Page-Table-Search Flow
206
Page Table Updates
207
Segment Register Updates
207
6 Instruction Timing
209
Terminology and Conventions
209
Instruction Timing Overview
211
Figure 6-1. Pipelined Execution Unit
212
Figure 6-2. Superscalar/Pipeline Diagram
212
Figure 6-3. Powerpc 750GX Microprocessor Pipeline Stages
214
Table 6-1. Notation Conventions for Instruction Timing
214
Timing Considerations
215
General Instruction Flow
215
Instruction Fetch Timing
216
Cache Arbitration
217
Cache Hit
217
Figure 6-4. Instruction Flow Diagram
218
Figure 6-5. Instruction Timing-Cache Hit
220
Cache Miss
222
Figure 6-6. Instruction Timing-Cache Miss
223
Instruction Dispatch and Completion Considerations
224
L2 Cache Access Timing Considerations
224
Rename Register Operation
224
Instruction Serialization
225
Execution-Unit Timings
225
Branch Processing Unit Execution Timing
225
Branch Folding
226
Branch Instructions and Completion
227
Figure 6-7. Branch Taken
227
Figure 6-8. Removal of Fall-Through Branch Instruction
227
Branch Prediction and Resolution
228
Figure 6-9. Branch Completion
228
Figure 6-10. Branch Instruction Timing
231
Effect of Floating-Point Exceptions on Performance
232
Floating-Point Unit Execution Timing
232
Integer Unit Execution Timing
232
Effect of Operand Placement on Performance
233
Load/Store Unit Execution Timing
233
Table 6-2. Performance Effects of Memory Operand Placement
233
Integer Store Gathering
234
System Register Unit Execution Timing
234
Memory Performance Considerations
235
Caching and Memory Coherency
235
Effect of TLB Miss
236
Instruction Scheduling Guidelines
236
Table 6-3. TLB Miss Latencies
236
Branch, Dispatch, and Completion-Unit Resource Requirements
237
Branch-Resolution Resource Requirements
237
Completion-Unit Resource Requirements
237
Dispatch-Unit Resource Requirements
237
Instruction Latency Summary
238
Table 6-4. Branch Instructions
238
Table 6-5. System-Register Instructions
238
Table 6-6. Condition Register Logical Instructions
240
Table 6-7. Integer Instructions
240
Table 6-8. Floating-Point Instructions
242
Table 6-9. Load-And-Store Instructions
244
7 Signal Descriptions
249
Signal Configuration
250
Figure 7-1. 750GX Signal Groups
250
Signal Descriptions
251
Address-Bus Arbitration Signals
251
Bus Request (BR)-Output
251
Address Bus Busy (ABB)
252
Bus Grant (BG)-Input
252
Address Transfer Start Signals
253
Transfer Start (TS)
253
Address Transfer Signals
254
Address Bus (A[0-31])
254
Address-Bus Parity (AP[0-3])
255
Address Transfer Attribute Signals
255
Table 7-1. Transfer Type Encodings for Powerpc 750GX Bus Master
256
Transfer Type (TT[0-4])
256
Table 7-2. Powerpc 750GX Snoop Hit Response
257
Transfer Size (TSIZ[0-2])-Output
258
Table 7-3. Data-Transfer Size
259
Transfer Burst (TBST)
259
Cache Inhibit (CI)-Output
260
Write-Through (WT)-Output
260
Global (GBL)
261
Address Transfer Termination Signals
262
Address Acknowledge (AACK)-Input
262
Address Retry (ARTRY)
263
Data-Bus Arbitration Signals
264
Data-Bus Grant (DBG)-Input
264
Data Bus Busy (DBB)
265
Data-Bus Write-Only (DBWO)
265
Data-Transfer Signals
266
Data Bus (DH[0-31], DL[0-31])
266
Table 7-4. Data-Bus Lane Assignments
266
Data-Bus Parity (DP[0-7])
267
Table 7-5. DP[0-7] Signal Assignments
267
Data Bus Disable (DBDIS)-Input
268
Data-Transfer Termination Signals
268
Transfer Acknowledge (TA)-Input
268
Data Retry (DRTRY)-Input
269
Table 7-6. Summary of Mode Select Signals
269
Transfer Error Acknowledge (TEA)-Input
269
System Status Signals
270
Interrupt (INT)- Input
270
System Management Interrupt (SMI)-Input
270
Checkstop Input (CKSTP_IN)-Input
271
Checkstop Output (CKSTP_OUT)-Output
271
Machine-Check Interrupt (MCP)-Input
271
Reset Signals
272
Hard Reset (HRESET)-Input
272
Soft Reset (SRESET)-Input
272
Processor Status Signals
273
Quiescent Acknowledge (QACK)-Input
273
Quiescent Request (QREQ)-Output
273
Reservation (RSRV)-Output
273
Processor Mode Selection Signals
274
Time Base Enable (TBEN)-Input
274
TLB Invalidate Synchronize (TLBISYNC)-Input
274
I/O Voltage Select Signals
275
IEEE 1149.1A-1993 Interface Description
275
Lssd_Mode
275
Table 7-7. Bus Voltage Selection Settings
275
Table 7-8. IEEE Interface Pin Descriptions
275
Test Interface Signals
275
Bvsel
276
Clock Signals
276
L1_Tstclk
276
L2_Tstclk
276
Clock out (CLK_OUT)-Output
277
PLL Configuration (PLL_CFG[0:4])-Input
277
System Clock (SYSCLK)-Input
277
PLL Range (PLL_RNG[0:1])-Input
278
Power and Ground Signals
278
8 Bus Interface Operation
279
Bus Interface Overview
280
Figure 8-1. Bus Interface Address Buffers
280
Operation of the Instruction and Data L1 Caches
281
Bus Signal Clocking
282
Operation of the Bus Interface
282
Optional 32-Bit Data Bus Mode
282
Direct-Store Accesses
283
Figure 8-2. Timing Diagram Legend
283
Memory-Access Protocol
284
Figure 8-3. Overlapping Tenures on the 750GX Bus for a Single-Beat Transfer
284
Arbitration Signals
285
Figure 8-4. Cache Diagram for Miss-Under-Miss Feature
286
Miss-Under-Miss
286
Figure 8-5. First Level Address Pipelining
287
Miss-Under-Miss and System Performance
287
Speculative Loads and Conditional Branches
290
Address-Bus Tenure
290
Address-Bus Arbitration
290
Figure 8-6. Address-Bus Arbitration
290
Figure 8-7. Address-Bus Arbitration Showing Bus Parking
291
Address Transfer
292
Figure 8-8. Address-Bus Transfer
293
Address Transfer Attribute Signals
294
Address-Bus Parity
294
Table 8-1. Transfer Size Signal Encodings
294
Burst Ordering During Data Transfers
295
Table 8-2. Burst Ordering-64-Bit Bus
295
Effect of Alignment in Data Transfers
296
Table 8-3. Burst Ordering-32-Bit Bus
296
Table 8-4. Aligned Data Transfers
296
Table 8-5. Misaligned Data Transfers (4-Byte Examples)
298
Table 8-6. Aligned Data Transfers (32-Bit Bus Mode)
298
Table 8-7. Misaligned 32-Bit Data-Bus Transfer (4-Byte Examples)
299
Address Transfer Termination
300
Alignment of External Control Instructions
300
Data-Bus Tenure
301
Data-Bus Arbitration
301
Figure 8-9. Snooped Address Cycle with ARTRY
301
Figure 8-10. Data-Bus Arbitration
302
Using the DBB Signal
302
Data Transfer
303
Data-Bus Write-Only
303
Data-Transfer Termination
303
Figure 8-11. Normal Single-Beat Read Termination
304
Normal Single-Beat Termination
304
Figure 8-12. Normal Single-Beat Write Termination
305
Figure 8-13. Normal Burst Transaction
305
Figure 8-14. Termination with DRTRY
306
Data-Transfer Termination Due to a Bus Error
307
Figure 8-15. Read Burst with TA Wait States and DRTRY
307
Memory Coherency-MEI Protocol
308
Figure 8-16. MEI Cache-Coherency Protocol-State Diagram (WIM = 001)
309
Timing Examples
309
Figure 8-17. Fastest Single-Beat Reads
310
Figure 8-18. Fastest Single-Beat Writes
311
Figure 8-19. Single-Beat Reads Showing Data-Delay Controls
312
Figure 8-20. Single-Beat Writes Showing Data-Delay Controls
313
Figure 8-21. Burst Transfers with Data-Delay Controls
314
Figure 8-22. Use of Transfer Error Acknowledge (TEA)
315
Optional Bus Configuration
316
32-Bit Data Bus Mode
316
Figure 8-23. 32-Bit Data-Bus Transfer (8-Beat Burst)
317
Figure 8-24. 32-Bit Data-Bus Transfer (2-Beat Burst with DRTRY)
317
No-DRTRY Mode
318
Processor State Signals
319
Support for the Lwarx and Stwcx. Instruction Pair
319
TLBISYNC Input
319
IEEE 1149.1A-1993 Compliant Interface
319
JTAG/COP Interface
319
Using Data-Bus Write-Only
320
Figure 8-25. IEEE 1149.1A-1993 Compliant Boundary-Scan Interface
320
Figure 8-26. Data-Bus Write-Only Transaction
320
9 L2 Cache
323
L2 Cache Overview
323
L2 Cache Operation
323
Table 9-1. Interpretation of LRU Bits
324
Table 9-2. Modification of LRU Bits
325
Table 9-3. Effect of Locked Ways on LRU Interpretation
325
Figure 9-1. L2 Cache
327
L2 Cache Control Register (L2CR)
329
L2 Cache Initialization
329
L2 Cache Global Invalidation
329
L2 Cache Used as On-Chip Memory
330
Locking the L2 Cache
330
Loading the Locked L2 Cache
331
Locked Cache Operation
331
Data-Only and Instruction-Only Modes
332
L2 Cache Test Features and Methods
332
L2CR Support for L2 Cache Testing
332
L2 Cache Testing
333
L2 Cache Timing
333
10 Power and Thermal Management
335
Dynamic Power Management
335
Programmable Power Modes
335
Figure 10-1. 750GX Power States
336
Table 10-1. 750GX Microprocessor Programmable Power Modes
336
Power Management Modes
337
Doze Mode
337
Full on Mode
337
Nap Mode
337
Table 10-2. HID0 Power Saving Mode Bit Settings
337
Dynamic Power Reduction
339
Sleep Mode
339
Power Management Software Considerations
340
750GX Dual PLL Feature
340
Overview
340
Configuration Restriction on Frequency Transitions
341
Dual PLL Implementation
342
Figure 10-2. Dual PLL Block Diagram
342
Thermal Assist Unit
343
Thermal Assist Unit Overview
343
Figure 10-3. Dual PLL Switching Example, 3X to 4X
343
Thermal Assist Unit Operation
344
Figure 10-4. Thermal Assist Unit Block Diagram
344
Table 10-3. Valid THRM1 and THRM2 Bit Settings
345
TAU Single-Threshold Mode
345
750GX Junction Temperature Determination
346
TAU Dual-Threshold Mode
346
Power Saving Modes and TAU Operation
347
Instruction-Cache Throttling
347
Figure 10-5. Instruction Cache Throttling Control SPR Diagram
347
Table 10-4. ICTC Bit Field Settings
348
11 Performance Monitor and System Related Features
349
Performance-Monitor Interrupt
349
Special-Purpose Registers Used by Performance Monitor
350
Table 11-1. Performance Monitor Sprs
350
Performance-Monitor Registers
351
Monitor Mode Control Register 0 (MMCR0)
351
Monitor Mode Control Register 1 (MMCR1)
351
Performance-Monitor Counter Registers (Pmcn)
351
User Monitor Mode Control Register 0 (UMMCR0)
351
User Monitor Mode Control Register 1 (UMMCR1)
351
Table 11-2. PMC1 Events-MMCR0[19:25] Select Encodings
352
Table 11-3. PMC2 Events-MMCR0[26:31] Select Encodings
352
Table 11-4. PMC3 Events-MMCR1[0:4] Select Encodings
353
Table 11-5. PMC4 Events-MMCR1[5:9] Select Encodings
354
User Performance-Monitor Counter Registers (UPMC1-UPMC4)
354
Sampled Instruction Address Register (SIA)
355
User Sampled Instruction Address Register (USIA)
355
Event Counting
355
Event Selection
356
Notes
356
Debug Support
357
Data-Address Breakpoint
357
Overview
357
JTAG/COP Functions
357
Introduction
357
Processor Resources Available through JTAG/COP Serial Interface
357
Figure 11-1. 750GX IEEE 1149.1A-1993/COP Organization
358
Resets
359
Hard Reset
359
Soft Reset
359
Figure 11-2. Reset Sequence
360
Reset Sequence
360
Checkstops
361
Checkstop Control Bits
361
Checkstop Sources
361
Table 11-6. HID0 Checkstop Control Bits
361
Open-Collector-Driver States During Checkstop
362
Vacancy Slot Application
362
750GX Parity
363
Enabling Parity Error Detection
364
Parity Control and Status
364
Parity Errors
364
Acronyms and Abbreviations
365
Index
369
Revision Log
377
4
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IBM PowerPC 750GX Specifications
General
Brand
IBM
Model
PowerPC 750GX
Category
Computer Hardware
Language
English
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