IBM PowerPC 750GX

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
750gx_umTOC.fm.(1.2)
March 27, 2006
Page 7 of 377
5.1.8 MMU Instructions and Register Summary ........................................................................... 194
5.2 Real-Addressing Mode .................................................................................................................. 195
5.3 Block-Address Translation ............................................................................................................ 196
5.4 Memory Segment Model ............................................................................................................... 196
5.4.1 Page History Recording ....................................................................................................... 196
5.4.1.1 Referenced Bit .............................................................................................................. 197
5.4.1.2 Changed Bit .................................................................................................................. 198
5.4.1.3 Scenarios for Referenced and Changed Bit Recording ............................................... 198
5.4.2 Page Memory Protection ..................................................................................................... 199
5.4.3 TLB Description ................................................................................................................... 199
5.4.3.1 TLB Organization ......................................................................................................... 199
5.4.3.2 TLB Invalidation ............................................................................................................ 201
5.4.4 Page-Address-Translation Summary .................................................................................. 202
5.4.5 Page Table-Search Operation ............................................................................................. 204
5.4.6 Page Table Updates ............................................................................................................ 207
5.4.7 Segment Register Updates ................................................................................................. 207
6. Instruction Timing ................................................................................................... 209
6.1 Terminology and Conventions ...................................................................................................... 209
6.2 Instruction Timing Overview .......................................................................................................... 211
6.3 Timing Considerations .................................................................................................................. 215
6.3.1 General Instruction Flow ...................................................................................................... 215
6.3.2 Instruction Fetch Timing ...................................................................................................... 216
6.3.2.1 Cache Arbitration .......................................................................................................... 217
6.3.2.2 Cache Hit ...................................................................................................................... 217
6.3.2.3 Cache Miss ................................................................................................................... 222
6.3.2.4 L2 Cache Access Timing Considerations ..................................................................... 224
6.3.2.5 Instruction Dispatch and Completion Considerations ................................................... 224
6.3.2.6 Rename Register Operation ......................................................................................... 224
6.3.2.7 Instruction Serialization ................................................................................................ 225
6.4 Execution-Unit Timings ................................................................................................................. 225
6.4.1 Branch Processing Unit Execution Timing .......................................................................... 225
6.4.1.1 Branch Folding ............................................................................................................. 226
6.4.1.2 Branch Instructions and Completion ............................................................................ 227
6.4.1.3 Branch Prediction and Resolution ................................................................................ 228
6.4.2 Integer Unit Execution Timing ............................................................................................. 232
6.4.3 Floating-Point Unit Execution Timing .................................................................................. 232
6.4.4 Effect of Floating-Point Exceptions on Performance ........................................................... 232
6.4.5 Load/Store Unit Execution Timing ....................................................................................... 233
6.4.6 Effect of Operand Placement on Performance .................................................................... 233
6.4.7 Integer Store Gathering ....................................................................................................... 234
6.4.8 System Register Unit Execution Timing .............................................................................. 234
6.5 Memory Performance Considerations ........................................................................................... 235
6.5.1 Caching and Memory Coherency ........................................................................................ 235
6.5.2 Effect of TLB Miss ............................................................................................................... 236
6.6 Instruction Scheduling Guidelines ................................................................................................. 236
6.6.1 Branch, Dispatch, and Completion-Unit Resource Requirements ....................................... 237
6.6.1.1 Branch-Resolution Resource Requirements ................................................................ 237
6.6.1.2 Dispatch-Unit Resource Requirements ........................................................................ 237