User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
750gx_umTOC.fm.(1.2)
March 27, 2006
Page 9 of 377
7.2.11.4 Time Base Enable (TBEN)—Input ............................................................................. 274
7.2.11.5 TLB Invalidate Synchronize (TLBISYNC
)—Input ....................................................... 274
7.2.12 Processor Mode Selection Signals .................................................................................... 274
7.2.13 I/O Voltage Select Signals ................................................................................................. 275
7.2.14 Test Interface Signals ........................................................................................................ 275
7.2.14.1 IEEE 1149.1a-1993 Interface Description .................................................................. 275
7.2.14.2 L
SSD_MODE ............................................................................................................. 275
7.2.14.3 L1_TSTCLK ................................................................................................................ 276
7.2.14.4 L2_TSTCLK ................................................................................................................ 276
7.2.14.5 BVSEL ........................................................................................................................ 276
7.2.15 Clock Signals ..................................................................................................................... 276
7.2.15.1 System Clock (SYSCLK)—Input ................................................................................ 277
7.2.15.2 Clock Out (CLK_OUT)—Output ................................................................................. 277
7.2.15.3 PLL Configuration (PLL_CFG[0:4])—Input ................................................................. 277
7.2.15.4 PLL Range (PLL_RNG[0:1])—Input ........................................................................... 278
7.2.16 Power and Ground Signals ................................................................................................ 278
8. Bus Interface Operation ......................................................................................... 279
8.1 Bus Interface Overview ................................................................................................................. 280
8.1.1 Operation of the Instruction and Data L1 Caches ............................................................... 281
8.1.2 Operation of the Bus Interface ............................................................................................. 282
8.1.3 Bus Signal Clocking ............................................................................................................. 282
8.1.4 Optional 32-Bit Data Bus Mode ........................................................................................... 282
8.1.5 Direct-Store Accesses ......................................................................................................... 283
8.2 Memory-Access Protocol .............................................................................................................. 284
8.2.1 Arbitration Signals ............................................................................................................... 285
8.2.2 Miss-under-Miss .................................................................................................................. 286
8.2.2.1 Miss-under-Miss and System Performance ................................................................. 287
8.2.2.2 Speculative Loads and Conditional Branches .............................................................. 290
8.3 Address-Bus Tenure ..................................................................................................................... 290
8.3.1 Address-Bus Arbitration ....................................................................................................... 290
8.3.2 Address Transfer ................................................................................................................. 292
8.3.2.1 Address-Bus Parity ....................................................................................................... 294
8.3.2.2 Address Transfer Attribute Signals ............................................................................... 294
8.3.2.3 Burst Ordering During Data Transfers .......................................................................... 295
8.3.2.4 Effect of Alignment in Data Transfers ........................................................................... 296
8.3.2.5 Alignment of External Control Instructions ................................................................... 300
8.3.3 Address Transfer Termination ............................................................................................. 300
8.4 Data-Bus Tenure ........................................................................................................................... 301
8.4.1 Data-Bus Arbitration ............................................................................................................ 301
8.4.1.1 Using the DBB
Signal ................................................................................................... 302
8.4.2 Data-Bus Write-Only ............................................................................................................ 303
8.4.3 Data Transfer ....................................................................................................................... 303
8.4.4 Data-Transfer Termination .................................................................................................. 303
8.4.4.1 Normal Single-Beat Termination .................................................................................. 304
8.4.4.2 Data-Transfer Termination Due to a Bus Error ............................................................ 307
8.4.5 Memory Coherency—MEI Protocol ..................................................................................... 308
8.5 Timing Examples ........................................................................................................................... 309
8.6 Optional Bus Configuration ........................................................................................................... 316
8.6.1 32-Bit Data Bus Mode ......................................................................................................... 316
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