Inovance SV820N Series - Page 95

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5 Troubleshooting
5
■ E3.102: Abnormal communication initialization of coprocessor
Cause:
Multi-core communication initialization fault or software version of cores not matching
Probable Cause ConrmingMethod Corrective Action
1. The FPGA software
version and the
software version of
CPU cores do not
match.
View the FPGA software version (2001-03h) and the
CUP0 software version (2001-04h) and the CUP1 software
version(2001-05h)viathekeypadortheInovanceservo
commissioningsoftware.Checkwhetherthenon-zero
valueofthemostsignicantbitisthesameinthetwo
versions.
Contact Inovance for
technical support. Update
thesoftwaretomakethem
match.
2. The FPGA is faulty.
The fault persists after the servo drive is powered off and
on for several times.
Replace the servo drive.
■ E3.104: Abnormal communication or interrupt timeout of coprocessor
Cause:
Coprocessor or FPGA interrupt timeout, cyclic access among coprocessors timeout
Probable Cause ConrmingMethod Corrective Action
1. The FPGA is faulty.
The fault persists after the servo drive
is powered off and on several times.
Replace the servo drive.
2. Thecommunicationhandshakebetween
the FPGA and the MCU is abnormal.
3. MCU interrupt times out.
■ E3.105: Internal program abnormal
Cause:
The total number of parameters is abnormal at EEPROM reading/writing operation.
The data range of parameters is abnormal, which generally occurs after software updates.
Probable Cause ConrmingMethod Corrective Action
1. An EEPROM fault occurs.
Checkthecausesaccordingtothe
method of E3.101.
Restore the default setting (2002-
20h=1), and power on the system
again.
2. The servo drive is faulty.
The fault persists after the servo drive is
powered off and on several times.
Replace the servo drive.
■ E3.106: abnormal communication of the main processor
To distinguish the fault symptom, the servo drive displays different internal fault codes under the same fault
code. You can view these internal fault codes in 200B-2Eh.
Cause:
Access between HOST and FPGA or between Host and coprocessor times out during power-on initialization.
Probable Cause ConrmingMethod Corrective Action
1. The FPGA is faulty.
The fault persists after the servo drive
is powered off and on several times.
Replace the servo drive.
2. Thecommunicationhandshakebetween
the FPGA and the HOST is abnormal.
3. Access between HOST and coprocessor
times out.