Intel Cyclone V User Manual

If the HPS Flash Programmer tool is to be used, confirm that it supports the device
you are planning to use. The supported devices are listed in the Intel SoC FPGA
Embedded Development Suite User Guide.
Other ways to program the flash devices are:
• Program Flash using a debugger (for example DS-5)
• Program Flash from U-Boot
• Program Flash from Linux (or other OS) console
• Program Flash by means of dedicated hardware
Related Information
Intel
®
SoC FPGA Embedded Development Suite User Guide
4.2.1.8. For QSPI and SD/MMC/eMMC Provide Flash Memory Reset
GUIDELINE: Ensure that the QSPI and SD/MMC/eMMC devices have a
mechanism to be reset when the HPS is reset.
The QSPI and SD/MMC/eMMC flash devices can potentially be put in a state by
software where the BootROM cannot access them successfully, which may trigger a
boot failure on the next reset. This problem can occur because the HPS is reset, but
the flash part is not reset.
It is therefore required to reset the QSPI and SD/MMC/eMMC boot flash devices each
time there is an HPS reset (warm or cold).
Note that some devices do not have a reset pin. In such a case, you must power-cycle
the flash by other means, for example with a MOSFET. Pay attention to minimum
required reset pulse duration.
4.2.1.9. Selecting QSPI Flash Devices
GUIDELINE: For bare-metal applications, avoid using a QSPI flash device
larger than 16 MB
QSPI flash devices of 16 MB or less always support three-byte addressing. Therefore,
they are accessible to the HPS Boot ROM. With such devices, you do not need to reset
or power-cycle the flash when the HPS undergoes cold or warm reset.
GUIDELINE: With a QSPI device larger than 16 MB, use QSPI extended 4-byte
addressing commands if supported by the device
Some QSPI flash devices support an extended command set, allowing the master to
use four-byte addressing without switching to four-byte addressing mode. If you use
the extended command set, you can leave the flash device in three-byte addressing
mode, so that the Boot ROM can access it on the next reset cycle without resetting or
power-cycling the flash device.
For detailed information about booting from QSPI, refer to CV SoC and AV Soc QSPI
Boot on RocketBoards.org.
4. Board Design Guidelines for SoC FPGAs
AN-796 | 2018.06.18
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
31

Intel Cyclone V Specifications

General

FPGA Family	Cyclone V
Logic Elements	25K to 301K
Transceivers	Up to 12
Processor	Dual-core ARM Cortex-A9
Process Technology	28 nm
Embedded Memory	M10K blocks
Operating Temperature	0°C to +85°C (Commercial), -40°C to +100°C (Industrial), -40°C to +125°C (Automotive)
Power Consumption	Varies by configuration and usage
Maximum User I/O	Up to 524