The only HPS I/O constraints you must manage are for HPS Dedicated Function Pins
and HPS Dedicated I/O. Constraints such as drive strength, I/O standards, and weak
pull-up enables are added to the Intel Quartus Prime project just like FPGA constraints
and are applied to the HPS at boot time when the second stage bootloader configures
the I/O. For FPGA I/O, the I/O constraints are applied to the FPGA configuration file.
Note: During power up, the HPS Dedicated I/O required for boot flash devices are configured
by the Boot ROM, depending on the BSEL values.
3.3. HPS Clocking and Reset Design Considerations
The main clock and resets for the HPS subsystem are HPS_CLK1, HPS_CLK2,
HPS_nPOR, HPS_nRST and HPS_PORSEL. HPS_CLK1 sources the Main PLL that
generates the clocks for the MPU, L3/L4 sub-systems, debug sub-system and the
Flash controllers. It can also be programmed to drive the Peripheral and SDRAM PLLs.
HPS_CLK2 meanwhile can be used as an alternative clock source to the Peripheral and
the SDRAM PLLs.
HPS_nPOR provides a cold reset input, and HPS_nRST provides a bidirectional warm
reset resource. As for the HPS_PORSEL, it is an input pin that can be used to select
either a standard POR delay or a fast POR delay for the HPS block.
Note: Refer to the Cyclone V Device Family Pin Connection Guidelines or Arria V GT, GX, ST,
and SX Device Family Pin Connection Guidelines for more information on connecting
the HPS clock and reset pins.
3. Design Guidelines for HPS portion of SoC FPGAs
AN-796 | 2018.06.18
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
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