5.3.4. ECC for Flash Memory
All peripheral RAMs in the HPS subsystem are ECC protected. The NAND flash
controller ECC hardware is not used when a read-modify-write operation is performed
from the flash device’s page buffer. Software must update the ECC during such read-
modify-write operations. For a read-modify-write operation to work with hardware
ECC, the entire page must be read into system memory, modified, then written back
to flash without relying on the flash device’s read-modify-write feature.
The NAND flash controller cannot do ECC validation during a copy-back command. The
flash controller copies the ECC data but does not validate it during the copy operation.
5.4. HPS SDRAM Considerations
5.4.1. Using the Preloader To Debug the HPS SDRAM
To debug the HPS EMIF, you can change the settings in the preloader to enable
runtime calibration report, debug level information and check the status of HPS
SDRAM PLL.
Note: Refer to "Building the Second Stage Bootloader" in the Intel SoC FPGA Embedded
Development Suite User Guide for step-by-step instructions for compiling the
preloader.
Related Information
Intel
®
SoC FPGA Embedded Development Suite User Guide
5.4.1.1. Enable Runtime Calibration Report
To enable the runtime calibration report, use your preferred editor to open the
<project_folder>\software\spl_bsp\uboot-socfpga\board\altera
\socfpga\sdram\sequencer_defines.h file and configure the
RUNTIME_CAL_REPORT value to 1.
5. Embedded Software Design Guidelines for SoC FPGAs
AN-796 | 2018.06.18
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
63
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