3.3.1. HPS Clock Planning
GUIDELINE: Verify MPU and peripheral clocking using Platform Designer
(Standard)
Use Platform Designer (Standard) to initially define your HPS component
configuration. Set the HPS input clocks, and peripheral source clocks and frequencies.
Note any Platform Designer (Standard) warning or error messages. You can address
them by modifying clock settings. In some cases you might determine that a
particular warning condition does not impact your application.
3.3.2. Early Pin Planning and I/O Assignment Analysis
GUIDELINE: Choose an I/O voltage level for the HPS Dedicated Function I/O
HPS_CLK1, HPS_CLK2, HPS_nPOR and HPS_nRST are powered by
VCCRSTCLK_HPS. These HPS Dedicated Function Pins are LVCMOS/LVTTL at either
3.3V, 3.0V, 2.5V or 1.8V. The I/O signaling voltage for these pins are determined by
the supply level applied to VCCRSTCLK_HPS.
Note:
HPS_PORSEL can be connected to either VCCRSTCLK_HPS (for fast HPS POR delay) or
GND (for standard HPS POR delay).
Note:
VCCRSTCLK_HPS can share the same power and regulator with VCCIO_HPS and
VCCPD_HPS if they share the same voltage requirement. The functionality of powering
down the FPGA fabric, while keeping the HPS running, is not needed.
3.3.3. Pin Features and Connections for HPS JTAG, Clocks, Reset and PoR
GUIDELINE: With the HPS in use (powered), supply a free running clock on
HPS_CLK1 for SoC device HPS JTAG access.
Access to the HPS JTAG requires an active clock source driving HPS_CLK1.
GUIDELINE: When daisy chaining the FPGA and HPS JTAG for a single device,
ensure that the HPS JTAG is first device in the chain (located before the FPGA
JTAG).
Placing the HPS JTAG before the FPGA JTAG allows the ARM DS-5 debugger to initiate
warm reset to the HPS. However, in case of cold reset the entire JTAG chain is broken
until the cold reset completes, as discussed in the next section.
GUIDELINE: Consider board design to isolate HPS JTAG interface
The HPS Test Access Port (TAP) controller is reset on a cold reset. If the HPS JTAG and
FPGA JTAG are daisy-chained together, the entire JTAG chain is broken until the cold
reset completes. If access to the JTAG chain is required during HPS cold reset, design
the board to allow HPS JTAG to be bypassed.
GUIDELINE: HPS_nRST is an open-drain, bidirectional dedicated warm reset
I/O.
HPS_nRST is an active low, open-drain-type, bidirectional I/O. Externally asserting a
logic low to the HPS_nRST pin initiates a warm reset of the HPS subsystem. HPS warm
and cold reset can also be asserted from internal sources such as software-initiated
3. Design Guidelines for HPS portion of SoC FPGAs
AN-796 | 2018.06.18
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
20
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