4.2.2. Configuration
The Cyclone V / Arria V SoC devices support two main type sof configuration flows:
• Traditional FPGA configuration
• HPS-initiated FPGA configuration
HPS-initiated configuration uses fast passive parallel (FPP) mode allowing the HPS to
configure the FPGA using storage locations accessible to the HPS such as QSPI,
SD/MMC and NAND flash. The FPGA configuration flows for the Cyclone V/Arria V SoC
are the same for the Cyclone V/Arria V FPGA devices where an external configuration
data source is connected to the control block in the FPGA.
4.2.2.1. Traditional Configuration
The traditional FPGA configuration flow is where the FPGA is configured by an external
source such as JTAG, active serial or fast passive parallel.
4.2.2.2. HPS Initiated Configuration
When the device is powered and the HPS begin executing the software in the boot
ROM, all the device I/O default to an input tri-state mode of operation. The boot ROM
configures the dedicated boot I/O based on the sampled BSEL pins.
4.2.3. Reference Materials
Refer to the following reference materials for additional information.
Related Information
• Intel
®
SoC FPGA Embedded Development Suite User Guide
• Support tab on Cyclone V SoCs
Cyclone V SoC documentation
• Support tab on Arria V SoCs
Arria V SoC documentation
• SoC Embedded Development Suite Getting Started Guides
• Golden System Reference Design (GSRD) User Manuals
• AN-709: HPS SoC Boot Guide - Cyclone V SoC Development Kit
4.3. HPS Power Design Considerations
For design considerations and recommendations on power consumption and thermal
analysis, SoC device pin connections, supply design and decoupling, refer to the Arria
V and Cyclone V Design Guidelines.
The following sections are supplemental for SoC devices.
Related Information
Arria V and Cyclone V Design Guidelines
4. Board Design Guidelines for SoC FPGAs
AN-796 | 2018.06.18
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
32
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