Intel Cyclone V User Manual

1.4. Overview of Embedded Software Design Guidelines for SoC
FPGA Design
Table 4. Embedded Software: Design Guidelines Overview
Stages of the Embedded Software
Design Flow
Guidelines Links
Operating System (OS) considerations OS considerations to meet your
application needs, including real time,
software reuse, support and ease of
use considerations
Selecting an Operating System for Your
Application on page 52
Boot Loader considerations Boot loader considerations to meet
your application needs. including GPL
requirements, and features.
Choosing Boot Loader Software on
page 58
Boot and Configuration Design
Considerations
Boot source, boot clock, boot fuses,
configuration flows
Boot and Configuration Design
Considerations on page 28
HPS ECC Considerations ECC for external SDRAM interface, L2
cache data memory, flash memory
HPS ECC Design Considerations on
page 61
HPS SDRAM Considerations Using Preloader to debug HPS SDRAM,
Accessing the HPS SDRAM
HPS SDRAM Considerations on page
63
1. Overview of the Design Guidelines for Cyclone
®
V SoC FPGAs and Arria
®
V SoC FPGAs
AN-796 | 2018.06.18
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
9

Intel Cyclone V Specifications

General

FPGA Family	Cyclone V
Logic Elements	25K to 301K
Transceivers	Up to 12
Processor	Dual-core ARM Cortex-A9
Process Technology	28 nm
Embedded Memory	M10K blocks
Operating Temperature	0°C to +85°C (Commercial), -40°C to +100°C (Industrial), -40°C to +125°C (Automotive)
Power Consumption	Varies by configuration and usage
Maximum User I/O	Up to 524