Intel Cyclone V - User Manual

AN 796: Cyclone V and Arria V SoC
Device Design Guidelines
Updated for Intel
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AN-796 | 2018.06.18
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Intel Cyclone V Specifications

General

FPGA Family	Cyclone V
Logic Elements	25K to 301K
Transceivers	Up to 12
Processor	Dual-core ARM Cortex-A9
Process Technology	28 nm
Embedded Memory	M10K blocks
Operating Temperature	0°C to +85°C (Commercial), -40°C to +100°C (Industrial), -40°C to +125°C (Automotive)
Power Consumption	Varies by configuration and usage
Maximum User I/O	Up to 524

Summary

Overview of the Design Guidelines for Cyclone V SoC FPGAs and Arria V SoC FPGAs

The SoC FPGA Designers Checklist

Checklist for SoC FPGA design steps and considerations.

Overview of HPS Design Guidelines for SoC FPGA design

Summary of design guidelines for the Hard Processor System (HPS) in SoC FPGAs.

Overview of Board Design Guidelines for SoC FPGA Design

Summary of board design guidelines for SoC FPGA devices.

Overview of Embedded Software Design Guidelines for SoC FPGA Design

Summary of design guidelines for embedded software on SoC FPGAs.

Background: Comparison between Cyclone V SoC FPGA and Arria V SoC FPGA HPS Subsystems

Guidelines for Interconnecting the HPS and FPGA

Guidelines for connecting the HPS and FPGA fabric for optimal design performance.

HPS-FPGA Bridges

Details on the HPS bridges connecting the HPS and FPGA fabric via AXI interfaces.

FPGA-to-HPS SDRAM Access

Guidelines for accessing HPS SDRAM from FPGA logic using specific interfaces.

Connecting Soft Logic to HPS Component

How to connect soft logic components to the HPS using Platform Designer.

Design Guidelines for HPS portion of SoC FPGAs

Start your SoC-FPGA design here

Initial steps and starting points for designing an SoC FPGA.

Design Considerations for Connecting Device I;O to HPS Peripherals and Memory

Understanding HPS I/O organization and design considerations for peripherals.

HPS Clocking and Reset Design Considerations

Guidelines for managing HPS clocking and reset signals for reliable operation.

HPS EMIF Design Considerations

Design considerations for the HPS External Memory Interface (EMIF) and SDRAM.

DMA Considerations

Guidelines for using Direct Memory Access (DMA) for system performance.

Managing Coherency for FPGA Accelerators

Managing data coherency between FPGA accelerators and the HPS.

IP Debug Tools

Overview of tools for debugging IP and system-level designs in FPGAs.

Board Design Guidelines for SoC FPGAs

Board Bring Up Considerations

Key considerations for bringing up the board during initial development.

Boot and Configuration Design Considerations

Guidelines for designing boot sources, configuration, and flash programming.

HPS Power Design Considerations

Recommendations for power consumption, thermal analysis, and power supplies for HPS.

Boundary Scan for HPS

Guidelines for performing boundary scan tests on HPS I/O.

Design Guidelines for HPS Interfaces

Design guidelines for various HPS interfaces like EMAC, USB, QSPI, etc.

Embedded Software Design Guidelines for SoC FPGAs

Embedded Software for HPS: Design Guidelines

Guidelines for developing embedded software for the HPS.

Flash Device Driver Design Considerations

Design considerations for flash device drivers supported by SoC FPGAs.

HPS ECC Design Considerations

Design considerations for Error Correction Code (ECC) implementation within the HPS.

HPS SDRAM Considerations

Considerations for HPS SDRAM, including debugging and access methods.

Support and Documentation

Support

Information on technical support provided for Intel SoC FPGA products and tools.

Software Documentation

Resources for software documentation, including community web hosting.

Additional Information

Cyclone V and Arria V SoC Device Guidelines Revision History

History of revisions and updates to the Cyclone V and Arria V SoC Device Guidelines.