Intel Cyclone V - Design Considerations for HPS and FPGA Power Supplies for Soc FPGA; Devices; Pin Connection Considerations for Board Designs

Related Information
Early Power Estimators (EPE) and Power Analyzer
4.3.2. Design Considerations for HPS and FPGA Power Supplies for SoC
FPGA devices
4.3.2.1. Consider the Need to Power Down the FPGA Portion While Keeping the
HPS Running
GUIDELINE: Use a separate programmable regulator for FPGA supply to
support powering down the FPGA while keeping the HPS running.
Cyclone V/Arria V SoC devices offer the ability to power down the FPGA while keeping
the HPS running. To do this, the FPGA V
CC
must be sourced from a programmable
regulator that supports a control interface such as I
2
C. The Cyclone V SoC
Development Kit is an example of a development board that supports this feature. You
can find information about the Cyclone V SoC Development Kit at Cyclone V SoC
Development Kit and Intel SoC FPGA Embedded Development Suite.
You can refer to the Cyclone V SoC Smart Configuration design example to understand
how to control the FPGA power supply regulator using the I
2
C connection from the
HPS.
4.3.2.2. Consider Desired HPS Boot Clock Frequency
Cyclone V / Arria V SoC devices support a HPS boot clock from 10-50 MHz in PLL
bypass mode, and up to 400MHz in PLL Locked mode. During power up or cold reset,
the boot ROM samples the value of the CSEL pins and if needed, configure the HPS
PLL to provide a faster boot clock frequency.
Refer to the table with CSEL options and corresponding external oscillator frequency in
the "Booting and Configuration" appendix of the appropriate Hard Processor System
Technical Reference Manual.
Related Information
• "Booting and Configuration" appendix of the Cyclone V Hard Processor System
Technical Reference Manual
• "Booting and Configuration" appendix of the Arria V Hard Processor System
Technical Reference Manual
4.3.3. Pin Connection Considerations for Board Designs
4.3.3.1. Device Power-Up
Power-Up and Power-Down Sequencing
Cyclone V/ Arria V SoC devices have the following additional power rails to consider
for power sequencing.
•
VCC_HPS
•
VCCPD_HPS
•
VCCIO_HPS
4. Board Design Guidelines for SoC FPGAs
AN-796 | 2018.06.18
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
34