Intel Cyclone V User Manual

GUIDELINE: Minimize reflections at PHY TX_CLK and EMAC RX_CLK inputs to
prevent double-clocking.
Be cognizant if the connection is routed as a “T” as signal integrity must be
maintained such that no double-edges are seen at REF_CLK loads. Ensure reflections
at REF_CLK loads are minimized to prevent double-clocking.
GUIDELINE: Use a Signal Integrity (SI) simulation tool.
It is fairly straightforward to run SI simulations on these unidirectional signals. These
signals are almost always point-to-point, so simply determining an appropriate series
resistor to place on each signal is usually enough. Many times, this resistor is not
necessary, but the device drive strength and trace lengths as well as topology should
be studied when making this determination.
4.5.2. USB Interface Design Guidelines
The Cyclone V/Arria V SoC Hard Processor system can connect its embedded USB
MACs directly to industry-standard USB 2.0 ULPI PHYs using the HPS Dedicated I/O
that support 1.8V, 2.5V, 3.0V and 3.3V I/O standards. No FPGA routing resources are
used and timing is fixed, which simplifies design. This guide describes the design
guidelines covering all supported speeds of PHY operation: High-Speed (HS) 480
Mbps, Full-Speed (FS) 12 Mbps, and Low-Speed (LS) 1.5 Mbps.
Note: In Cyclone V SoC U19 package (484 pins) only one USB controller is available.
GUIDELINE: Design the board to support both USB PHY modes where the
device supplies the clock versus where an external clock is the source.
The interface between the ULPI MAC and PHY on the Cyclone V/Arria V SoC consists of
DATA[7:0], DIR and NXT from the MAC to the PHY and STP from the MAC to the PHY.
Lastly a static clock of 60 MHz is driven from the PHY and is required for operation,
including some register accesses from the HPS to the USB MAC. Ensure the PHY
manufacturer recommendations for RESET and power-up are followed.
GUIDELINE: Ensure that the USB signal trace lengths are minimized.
At 60 MHz, the period is 16.67 ns and in that time, for example, the clock must travel
from the external PHY to the MAC and then the data and control signals must travel
from the MAC to the PHY. Because there is a round-trip delay, the maximum length of
the CLK and ULPI signals are important. Based on timing data the maximum length is
recommended to be less than 7 inches. This is based on a PHY with a 5 ns Tco
specification. If the specification is slower the total length must be shortened
accordingly.
GUIDELINE: Ensure that signal integrity is considered.
Signal integrity is also important but mostly on the CLK signal driven from the PHY to
the MAC in the HPS subsystem. Because these signals are point-to-point with a
maximum length, they can usually run unterminated but it is recommended to
simulate the traces to make sure the reflections are minimized. Using the 50-ohm
output setting from the FPGA is typically recommended unless the simulations show
otherwise. A similar setting should be used from the PHY vendor if possible.
4. Board Design Guidelines for SoC FPGAs
AN-796 | 2018.06.18
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
43

Intel Cyclone V Specifications

General

FPGA Family	Cyclone V
Logic Elements	25K to 301K
Transceivers	Up to 12
Processor	Dual-core ARM Cortex-A9
Process Technology	28 nm
Embedded Memory	M10K blocks
Operating Temperature	0°C to +85°C (Commercial), -40°C to +100°C (Industrial), -40°C to +125°C (Automotive)
Power Consumption	Varies by configuration and usage
Maximum User I/O	Up to 524

Summary

Overview of the Design Guidelines for Cyclone V SoC FPGAs and Arria V SoC FPGAs

The SoC FPGA Designer's Checklist

Checklist for SoC FPGA design steps and considerations.

Overview of HPS Design Guidelines for SoC FPGA design

Summary of design guidelines for the Hard Processor System (HPS) in SoC FPGAs.

Overview of Board Design Guidelines for SoC FPGA Design

Summary of board design guidelines for SoC FPGA devices.

Overview of Embedded Software Design Guidelines for SoC FPGA Design

Summary of design guidelines for embedded software on SoC FPGAs.

Background: Comparison between Cyclone V SoC FPGA and Arria V SoC FPGA HPS Subsystems

Guidelines for Interconnecting the HPS and FPGA

Guidelines for connecting the HPS and FPGA fabric for optimal design performance.

HPS-FPGA Bridges

Details on the HPS bridges connecting the HPS and FPGA fabric via AXI interfaces.

FPGA-to-HPS SDRAM Access

Guidelines for accessing HPS SDRAM from FPGA logic using specific interfaces.

Connecting Soft Logic to HPS Component

How to connect soft logic components to the HPS using Platform Designer.

Design Guidelines for HPS portion of SoC FPGAs

Start your SoC-FPGA design here

Initial steps and starting points for designing an SoC FPGA.

Design Considerations for Connecting Device I/O to HPS Peripherals and Memory

Understanding HPS I/O organization and design considerations for peripherals.

HPS Clocking and Reset Design Considerations

Guidelines for managing HPS clocking and reset signals for reliable operation.

HPS EMIF Design Considerations

Design considerations for the HPS External Memory Interface (EMIF) and SDRAM.

DMA Considerations

Guidelines for using Direct Memory Access (DMA) for system performance.

Managing Coherency for FPGA Accelerators

Managing data coherency between FPGA accelerators and the HPS.

IP Debug Tools

Overview of tools for debugging IP and system-level designs in FPGAs.

Board Design Guidelines for SoC FPGAs

Board Bring Up Considerations

Key considerations for bringing up the board during initial development.

Boot and Configuration Design Considerations

Guidelines for designing boot sources, configuration, and flash programming.

HPS Power Design Considerations

Recommendations for power consumption, thermal analysis, and power supplies for HPS.

Boundary Scan for HPS

Guidelines for performing boundary scan tests on HPS I/O.

Design Guidelines for HPS Interfaces

Design guidelines for various HPS interfaces like EMAC, USB, QSPI, etc.

Embedded Software Design Guidelines for SoC FPGAs

Embedded Software for HPS: Design Guidelines

Guidelines for developing embedded software for the HPS.

Flash Device Driver Design Considerations

Design considerations for flash device drivers supported by SoC FPGAs.

HPS ECC Design Considerations

Design considerations for Error Correction Code (ECC) implementation within the HPS.

HPS SDRAM Considerations

Considerations for HPS SDRAM, including debugging and access methods.

Support and Documentation

Support

Information on technical support provided for Intel SoC FPGA products and tools.

Software Documentation

Resources for software documentation, including community web hosting.

Additional Information

Cyclone V and Arria V SoC Device Guidelines Revision History

History of revisions and updates to the Cyclone V and Arria V SoC Device Guidelines.