2.1.3. Connecting Soft Logic to HPS Component
Designers can connect soft logic components to the HPS using the Cyclone V/Arria V
HPS component in Platform Designer (Standard).
Note: Refer to the "Introduction to the HPS Component" and "Instantiating the HPS
Component" chapters of the appropriate Hard Processor System Technical Reference
Manual to understand the interface and available options. To connect a FPGA soft IP
component to the HPS, Platform Designer (Standard) provides the component editor
tool. For more information, refer to the "Creating Platform Designer (Standard)
Components" chapter of the Intel
®
Quartus
®
Prime Standard Edition Handbook,
Volume 1: Design and Synthesis.
Note: When designing and configuring high bandwidth DMA masters and related buffering in
the FPGA core, refer to the DMA Considerations on page 24 section of this document.
The principles covered in that section apply to all high bandwidth DMA masters (for
example Platform Designer (Standard) DMA Controller components, integrated DMA
controllers in custom peripherals) and related buffering in the FPGA core that access
HPS resources (for example HPS SDRAM) through the FPGA-to-SDRAM and FPGA-to-
HPS bridge ports, not just tightly coupled Arm CPU accelerators.
Related Information
• Introduction to the HPS Component - Cyclone V Hard Processor System Technical
Reference Manual
• Instantiating the HPS Component - Cyclone V Hard Processor System Technical
Reference Manual
• Introduction to the HPS Component - Arria V Hard Processor System Technical
Reference Manual
• Instantiating the HPS Component - Arria V Hard Processor System Technical
Reference Manual
2. Background: Comparison between Cyclone V SoC FPGA and Arria V SoC FPGA HPS Subsystems
AN-796 | 2018.06.18
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
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