2. Background: Comparison between Cyclone V SoC FPGA
and Arria V SoC FPGA HPS Subsystems
While the HPS subsystems in Cyclone V SoC and Arria V SoC are architecturally
similar, there are a few differences in features as listed below.
HPS Features
Cyclone V SoC Arria V SoC
Maximum MPU Frequency Up to 925 MHz Up to 1.05 GHz
Controller Area Network (CAN) Yes No
Total HPS Dedicated I/O with Loaner capability Up to 67 94
(1)
Automotive Grade Option Yes No
Maximum supported DDR3 Frequency for HPS SDRAM 400 MHz 533 MHz
Related Information
Differences Among Intel SoC Device Families
2.1. Guidelines for Interconnecting the HPS and FPGA
The memory-mapped connectivity between the HPS and the FPGA fabric is a crucial
tool to maximize the performance of your design.
Design guidelines for the FPGA portion of your design are provided in the Arria V and
Cyclone V Design Guidelines.
Related Information
Arria V and Cyclone V Design Guidelines
2.1.1. HPS-FPGA Bridges
The HPS has three bridges that use memory-mapped interfaces to the FPGA based on
the Arm* Advanced Microcontroller Bus Architecture (AMBA*) Advanced eXtensible
Interface (AXI*). Their purpose determines the direction of each bridge.
(1)
You can only assign a maximum of 71 HPS I/O as Loaner I/O to the FPGA. For a detailed
comparison between the HPS subsystem for Cyclone V SoC and Arria V SoC, refer to
Differences Among Intel SoC Device Families.
AN-796 | 2018.06.18
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and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
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