Intel Cyclone V - Default Chapter; Table of Contents

Contents
1. Overview of the Design Guidelines for Cyclone
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V SoC FPGAs and Arria
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V SoC
FPGAs........................................................................................................................ 4
1.1. The SoC FPGA Designer’s Checklist.......................................................................... 5
1.2. Overview of HPS Design Guidelines for SoC FPGA design.............................................7
1.3. Overview of Board Design Guidelines for SoC FPGA Design..........................................8
1.4. Overview of Embedded Software Design Guidelines for SoC FPGA Design...................... 9
2. Background: Comparison between Cyclone V SoC FPGA and Arria V SoC FPGA HPS
Subsystems............................................................................................................. 10
2.1. Guidelines for Interconnecting the HPS and FPGA.....................................................10
2.1.1. HPS-FPGA Bridges....................................................................................10
2.1.2. FPGA-to-HPS SDRAM Access......................................................................12
2.1.3. Connecting Soft Logic to HPS Component....................................................14
3. Design Guidelines for HPS portion of SoC FPGAs...........................................................15
3.1. Start your SoC-FPGA design here...........................................................................15
3.1.1. Recommended Starting Point for HPS-to-FPGA Interface Design..................... 15
3.1.2. Determining your SoC FPGA Topology......................................................... 15
3.2. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory.........16
3.2.1. HPS Pin Assignment Design Considerations..................................................17
3.2.2. HPS I/O Settings: Constraints and Drive Strengths....................................... 18
3.3. HPS Clocking and Reset Design Considerations........................................................ 19
3.3.1. HPS Clock Planning.................................................................................. 20
3.3.2. Early Pin Planning and I/O Assignment Analysis........................................... 20
3.3.3. Pin Features and Connections for HPS JTAG, Clocks, Reset and PoR ............... 20
3.3.4. Internal Clocks........................................................................................ 21
3.4. HPS EMIF Design Considerations............................................................................21
3.4.1. Considerations for Connecting HPS to SDRAM.............................................. 21
3.4.2. HPS SDRAM I/O Locations.........................................................................23
3.4.3. Integrating the HPS EMIF with the SoC FPGA Device.....................................23
3.4.4. HPS Memory Debug................................................................................. 23
3.5. DMA Considerations............................................................................................. 24
3.5.1. Choosing a DMA Controller........................................................................ 24
3.5.2. Optimizing DMA Master Bandwidth through HPS Interconnect........................ 24
3.5.3. Timing Closure for FPGA Accelerators......................................................... 24
3.6. Managing Coherency for FPGA Accelerators............................................................. 25
3.6.1. Cache Coherency..................................................................................... 25
3.6.2. Coherency between FPGA Logic and HPS: Accelerator Coherency Port (ACP).... 25
3.6.3. Data Size Impacts ACP Performance........................................................... 25
3.6.4. FPGA Access to ACP via AXI or Avalon-MM...................................................26
3.6.5. Data Alignment for ACP and L2 Cache ECC accesses..................................... 26
3.7. IP Debug Tools.................................................................................................... 26
4. Board Design Guidelines for SoC FPGAs........................................................................ 28
4.1. Board Bring Up Considerations...............................................................................28
4.1.1. Reserved BSEL Setting............................................................................. 28
4.2. Boot and Configuration Design Considerations......................................................... 28
4.2.1. Boot Design Considerations....................................................................... 28
Contents
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
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