Intel Cyclone V User Manual

4.2.2. Configuration.......................................................................................... 32
4.2.3. Reference Materials..................................................................................32
4.3. HPS Power Design Considerations.......................................................................... 32
4.3.1. Early System and Board Planning...............................................................33
4.3.2. Design Considerations for HPS and FPGA Power Supplies for SoC FPGA
devices...................................................................................................34
4.3.3. Pin Connection Considerations for Board Designs..........................................34
4.3.4. Power Analysis and Optimization................................................................ 35
4.4. Boundary Scan for HPS.........................................................................................36
4.5. Design Guidelines for HPS Interfaces...................................................................... 36
4.5.1. HPS EMAC PHY Interfaces......................................................................... 36
4.5.2. USB Interface Design Guidelines................................................................ 43
4.5.3. QSPI Flash Interface Design Guidelines....................................................... 44
4.5.4. SD/MMC and eMMC Card Interface Design Guidelines................................... 45
4.5.5. NAND Flash Interface Design Guidelines......................................................46
4.5.6. UART Interface Design Guidelines...............................................................46
4.5.7. I
2
C Interface Design Guidelines..................................................................47
4.5.8. SPI Interface Design Guidelines................................................................. 47
5. Embedded Software Design Guidelines for SoC FPGAs.................................................. 49
5.1. Embedded Software for HPS: Design Guidelines.......................................................49
5.1.1. Assembling the Components of Your Software Development Platform..............49
5.1.2. Selecting an Operating System for Your Application...................................... 52
5.1.3. Assembling your Software Development Platform for Linux............................ 53
5.1.4. Assembling a Software Development Platform for a Bare-Metal Application...... 57
5.1.5. Assembling your Software Development Platform for a Partner OS or RTOS..... 58
5.1.6. Choosing Boot Loader Software................................................................. 58
5.1.7. Selecting Software Tools for Development, Debug and Trace.......................... 60
5.2. Flash Device Driver Design Considerations.............................................................. 61
5.3. HPS ECC Design Considerations............................................................................. 61
5.3.1. General ECC Design Considerations............................................................ 62
5.3.2. System-Level ECC Control, Status and Interrupt Management........................62
5.3.3. ECC for L2 Cache Data Memory................................................................. 62
5.3.4. ECC for Flash Memory.............................................................................. 63
5.4. HPS SDRAM Considerations...................................................................................63
5.4.1. Using the Preloader To Debug the HPS SDRAM............................................. 63
5.4.2. Access HPS SDRAM via the FPGA-to-SDRAM Interface...................................67
A. Support and Documentation......................................................................................... 69
A.1. Support..............................................................................................................69
A.2. Software Documentation.......................................................................................70
B. Additional Information................................................................................................. 71
B.1. Cyclone V and Arria V SoC Device Guidelines Revision History....................................71
Contents
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
3

Intel Cyclone V Specifications

General

FPGA Family	Cyclone V
Logic Elements	25K to 301K
Transceivers	Up to 12
Processor	Dual-core ARM Cortex-A9
Process Technology	28 nm
Embedded Memory	M10K blocks
Operating Temperature	0°C to +85°C (Commercial), -40°C to +100°C (Industrial), -40°C to +125°C (Automotive)
Power Consumption	Varies by configuration and usage
Maximum User I/O	Up to 524