GUIDELINE: Use the Intel HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge,
available in Platform Designer (Standard).
Configure the HPS component in Platform Designer (Standard) for an EMAC as “FPGA”
I/O instance. Do not export the resulting HPS component GMII signals in Platform
Designer (Standard). Instead, add the Intel HPS GMII to TSE 1000BASE-X/SGMII PCS
Bridge to the Platform Designer (Standard) subsystem and connect to the HPS
component’s GMII signals. The bridge uses the Intel HPS EMAC Interface Splitter in
Platform Designer (Standard) to split out the emac conduit from the HPS component
for use by the GMII bridge. The bridge instantiates the Intel Triple Speed Ethernet
(TSE) MAC, configured in 1000 BASE-X/SGMII PCS PHY-only mode (i.e., no soft MAC
component). See the Embedded Peripherals IP User Guide for information on how to
use the Intel HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge.
Note: Refer to the Cyclone V SGMII Example Design for hardware and software example of
this implementation.
4.5.1.2.5. MDIO
The MDIO PHY management bus has two signals per MAC: MDC and MDIO. MDC is the
clock output, which is not free running. At 2.5 MHz, it has a 400-ns minimum period.
MDIO is a bi-directional data signal with a High-Z bus turnaround period.
When the MAC writes to the PHY, the data is launched on the falling edge, meaning
there is 200 ns -10 ns = 190 ns for flight time, signal settling, and setup at the
receiver. Because data is not switched until the following negative edge, there is also
200 ns of hold time. These requirements are very easy to meet with almost any board
topology. When the MAC reads from the PHY, the PHY is responsible for outputting the
read data from 0 to 300 ns back to the MAC, leaving 100 ns less 10 ns setup time, or
90 ns for flight time, signal settling, and setup at the receiver. This requirement is also
very easy to meet.
GUIDELINE: Implement pull-up resistor on board for MDC/MDIO.
Both signals require an external pull-up resistor, typically 1K but PHY data-sheets may
vary.
GUIDELINE: Ensure interface timing is met.
There is a 10ns setup and hold requirement for MDIO for data with respect to MDC.
4.5.1.3. Common PHY Interface Design Considerations
4.5.1.3.1. Signal Integrity
GUIDELINE: Use appropriate board-level termination on PHY outputs.
Not many PHYs offer I/O tuning for their outputs to the Cyclone V/Arria V SoC, so it is
wise to double check this signal path with a simulator. Place a series resistor on each
signal near the PHY output pins to reduce the reflections if necessary.
4. Board Design Guidelines for SoC FPGAs
AN-796 | 2018.06.18
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
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