Intel® Server Board S1200SP Family Technical Product Specification
100
Note: When performing this test, the probe clips and capacitors should be located close to the load.
These are the timing requirements for the power supply operation. The output voltages must rise from 10%
to within regulation limits (T
vout_rise
) within 5 to 70ms. For 12VSB, it is allowed to rise from 1.0 to 25ms. All
outputs must rise monotonically. Table below shows the timing requirements for the power supply being
turned on and off via the AC input, with PSON held low and the PSON signal, with the AC input applied.
Table 59. Timing Requirements
Delay from AC being applied to
12VSBbeing within regulation.
Delay from AC being applied to all
output voltages being within
regulation.
Time 12V output voltage stays within
regulation after loss of AC at 70% load.
Delay from loss of AC to de-assertion
of PWOK
Delay from PSON# active to output
voltages within regulation limits.
Delay from PSON# deactivate to
PWOK being de-asserted.
Delay from output voltages within
regulation limits to PWOK asserted at
turn on.
Delay from PWOK de-asserted to
output voltages dropping out of
regulation limits.
Duration of PWOK being in the de-
asserted state during an off/on cycle
using AC or the PSON signal.
Delay from 12VSBbeing in regulation
to O/Ps being in regulation at AC turn
on.
Time the 12VSBoutput voltage stays
within regulation after loss of AC.
Note: The 12VSBoutput voltage rise time shall be from 1.0ms to 25ms
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