Intel S1400FP - 11.9 Intel Xeon Phi Coprocessor Management Sensors

System Event Log Troubleshooting Guide for EPSD Platforms Based on Intel
®
Xeon
®
Processor E5 4600/2600/2400/1600/1400 Product Families
Miscellaneous Events
Revision 1.1 Intel order number G90620-002 109
11.9 Intel
®
Xeon Phi
™
Coprocessor Management Sensors
The Intel
®
Xeon
®
Processor E5 4600/2600/2400/1600 Product Families BMC supports limited manageability of the Intel
®
Xeon Phi
™
Coprocessor adapter as described in this section. The Intel
®
Xeon Phi
™
Coprocessor adapter uses the Many Integrated Core (MIC)
architecture and the sensors are referred to as MIC sensors.
For each manageable Intel
®
Xeon Phi
™
Coprocessor adapter found in the system, the BMC automatically enables the associated
thermal margin sensors (0xC4-0xC7) and status sensors (0xA2, 0xA3, 0xA6, 0xA7).
11.9.1 Intel
®
Xeon Phi
™
Coprocessor (MIC) Thermal Margin Sensors
The management controller FW of the Intel
®
Xeon Phi
™
Coprocessor adapter provides an IPMI sensor that is read to get the
temperature data. The BMC then instantiates its own version of this sensor, which is used for fan speed control.
The thermal margin sensor is the difference between the Core Temp sensor value and the TControl value reported by the Intel
®
Xeon
Phi
™
Coprocessor adapter.
This sensor will not log events into the SEL.
11.9.2 Intel
®
Xeon Phi
™
Coprocessor (MIC) Status Sensors
Every time DC power is turned on, the BMC checks for Intel
®
Xeon Phi
™
Coprocessor adapters installed in the system. All compatible
cards will be enabled for management. The status sensor is a direct copy of the status sensor reported by the Intel
®
Xeon Phi
™
Coprocessor adapter.
Table 86: MIC Status Sensors - Typical Characteristics
Byte
Field
Description
11
Sensor Type
C0h = OEM defined
12
Sensor Number
A2h = MIC 1 Status
A3h = MIC 2 Status
A6h = MIC 3 Status
A7h = MIC 4 Status