Intel S1400FP - 7.5.2 Memory Address Parity Error

Memory Subsystem
System Event Log Troubleshooting Guide for EPSD Platforms Based on Intel
®
Xeon
®
Processor E5 4600/2600/2400/1600/1400 Product Families
78 Intel order number G90620-002 Revision 1.1
Event Trigger Offset
Description
Next Steps
Hex
Description
5. Consider replacing the DIMM as a preventative measure.
For multiple occurrences, replace the DIMM.
7.5.2 Memory Address Parity Error
Address Parity errors are errors detected in the memory addressing hardware. Because these affect the addressing of memory
contents, they can potentially lead to the same sort of failures as ECC errors. They are logged as a distinct type of error because
they affect memory addressing rather than memory contents, but otherwise they are treated exactly the same as Uncorrectable ECC
Errors. Address Parity errors are logged to the BMC SEL, with Event Data to identify the failing address by channel and DIMM to the
extent that it is possible to do so.
Table 65: Address Parity Error Sensor Typical Characteristics
Byte
Field
Description
8
9
Generator ID
0033h = BIOS SMI Handler
11
Sensor Type
0ch = Memory
12
Sensor Number
13h
13
Event Direction and
Event Type
[7] Event direction
0b = Assertion Event
1b = Deassertion Event
[6:0] Event Type = 6Fh (Sensor Specific)
14
Event Data 1
[7:6] – 10b = OEM code in Event Data 2
[5:4] – 10b = OEM code in Event Data 3
[3:0] – Event Trigger Offset = 2h
15
Event Data 2
[7:5] – Reserved. Set to 0.
[4] – Channel Information Validity Check:
0b = Channel Number in Event Data 3 Bits[4:3] is not valid
1b = Channel Number in Event Data 3 Bits[4:3] is valid
[3] – DIMM Information Validity Check:
0b = DIMM Slot ID in Event Data 3 Bits[2:0] is not valid