Intel S1400FP - Table 59: Memory RAS Configuration Status Sensor - Event Trigger Offset - Next Steps

System Event Log Troubleshooting Guide for EPSD Platforms Based on Intel
®
Xeon
®
Processor E5 4600/2600/2400/1600/1400 Product Families
Memory Subsystem
Revision 1.1 Intel order number G90620-002 71
Byte
Field
Description
13
Event Direction and
Event Type
[7] Event direction
0b = Assertion Event
1b = Deassertion Event
[6:0] Event Type = 09h (digital Discrete)
14
Event Data 1
[7:6] – 10b = OEM code in Event Data 2
[5:4] – 10b = OEM code in Event Data 3
[3:0] – Event Trigger Offset as described in Table 59
15
Event Data 2
RAS Configuration Error Type
[7:4] = Reserved
[3:0] = Configuration Error
0 = None
3 = Invalid DIMM Configuration for RAS Mode
All other values are reserved.
16
Event Data 3
RAS Mode Configured
[7:4] = Reserved
[3:0] = RAS Mode
0h = None (Independent Channel Mode)
1h = Mirroring Mode
2h = Lockstep Mode
4h = Rank Sparing Mode
Table 59: Memory RAS Configuration Status Sensor – Event Trigger Offset – Next Steps
Event Trigger Offset
Description
Next Steps
Hex
Description
01h
RAS configuration
enabled.
User enabled mirrored channel mode
in setup.
Informational event only.
00h
RAS configuration
disabled.
Mirrored channel mode is disabled
(either in setup or due to unavailability
of memory at post, in which case post
error 8500 is also logged).
1. If this event is accompanied by a post error 8500, there was a problem
applying the mirroring configuration to the memory. Check for other errors
related to the memory and troubleshoot accordingly.
2. If there is no post error, mirror mode was simply disabled in BIOS setup and
this should be considered informational only.