Intel S1400FP - Page 5

System Event Log Troubleshooting Guide for EPSD Platforms Based on Intel
®
Xeon
®
Processor E5
4600/2600/2400/1600/1400 Product Families Table of Contents
Revision 1.1 Intel order number G90620-002 v
5.2.1 Threshold-based Temperature Sensors ................................................................ 49
5.2.2 Thermal Margin Sensors ....................................................................................... 51
5.2.3 Processor Thermal Control Sensors ...................................................................... 53
5.2.4 Processor DTS Thermal Margin Sensors .............................................................. 55
5.2.5 Discrete Thermal Sensors ..................................................................................... 55
5.2.6 DIMM Thermal Trip Sensors .................................................................................. 57
5.3 System Air Flow Monitoring Sensor ....................................................................... 58
6. Processor Subsystem ........................................................................................................ 59
6.1 Processor Status Sensor ....................................................................................... 59
6.2 Catastrophic Error Sensor ..................................................................................... 61
6.3 CPU Missing Sensor .............................................................................................. 62
6.3.1 CPU Missing Sensor – Next Steps ........................................................................ 63
6.4 Quick Path Interconnect Sensors .......................................................................... 63
6.4.1 QPI Link Width Reduced Sensor ........................................................................... 63
6.4.2 QPI Correctable Error Sensor ................................................................................ 64
6.4.3 QPI Fatal Error and Fatal Error #2 ......................................................................... 65
6.5 Processor ERR2 Timeout Sensor .......................................................................... 67
6.5.1 Processor ERR2 Timeout – Next Steps ................................................................ 68
6.6 Processor MSID Mismatch Sensor ........................................................................ 68
6.6.1 Processor MSID Mismatch Sensor – Next Steps .................................................. 69
7. Memory Subsystem ........................................................................................................... 70
7.1 Memory RAS Configuration Status ........................................................................ 70
7.2 Memory RAS Mode Select .................................................................................... 72
7.3 Mirroring Redundancy State .................................................................................. 73
7.3.1 Mirroring Redundancy State Sensor – Next Steps ................................................ 74
7.4 Sparing Redundancy State .................................................................................... 74
7.4.1 Sparing Redundancy State Sensor – Next Steps .................................................. 76
7.5 ECC and Address Parity ........................................................................................ 76
7.5.1 Memory Correctable and Uncorrectable ECC Error .............................................. 76
7.5.2 Memory Address Parity Error ................................................................................ 78
8. PCI Express* and Legacy PCI Subsystem ....................................................................... 81
8.1 PCI Express* Errors ............................................................................................... 81
8.1.1 Legacy PCI Errors ................................................................................................. 81
8.1.2 PCI Express* Fatal Errors and Fatal Error #2 ........................................................ 82
8.1.3 PCI Express* Correctable Errors ........................................................................... 84
9. System BIOS Events .......................................................................................................... 87
9.1 System Events ....................................................................................................... 87
9.1.1 System Boot .......................................................................................................... 87
9.1.2 Timestamp Clock Synchronization ........................................................................ 87
9.2 System Firmware Progress (Formerly Post Error) ................................................. 89