Chapter 3 — Theory of Operation
70 CV30 Fixed Mount Computer Service Manual
Processor Address Decoder
The processor also has internal logic to provide programmable address
decode to select external devices on the bus. When not used as address
decode, these pins can be used as general purpose inputs or outputs.
Processor Bus Interface
The processor has the typical address and data buses along with a few
miscellaneous signals.
Main Bus Device
The main bus devices share the same data and address bus lines. Some
devices use different subsets of the address and data lines to accomplish
their functionality and each device may use the bus for longer or shorter
amounts of time depending upon their speed. The transceiver buffers
convert the signal level of portions of the main bus for connection to the
Wireless LAN and Ethernet. The processor address and data bus are 1.8 V
levels while the Wireless LAN and Ethernet controller address and data bus
are 3.3 V levels. Devices on the main bus are:
• Mobile SDRAM
• Flash ROM (DiskOnChip)
• Graphic controller
• Bus transceiver for Wireless LAN and Ethernet connection
Mobile SDRAM
The mobile SDRAM is the main memory used by the CPU to operate
applications. Power to this memory is provided continuously to prevent loss
of programs or data. There are two SRAM with a combined capacity of 64
MB.
The performance for the mobile SDRAM parts is:
• CL=2 @ 83 MHz or CL=3 @ 133 MHz
Signal Signal Description
nCS[1] nCS[1] Ethernet chip select
nCS[2] -
nCS[3] nVIDEO_CS Graphics contoller chip select
nCS[4] -
nCS[5] -
Signal Description
MA_LCL [25:0] Address bus, bi-directional
MC_LCL [32:0] Data bus, bi-directional
RDY Ready signal
nWE_LCL Write enable
nOE_LCL Output enable
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