Chapter 3 — Theory of Operation
CV30 Fixed Mount Computer Service Manual 71
We can utilize mobile SDRAM with different core voltage requirements
depending upon the board loading. Both 1.8 V and 2.5 V core parts can be
used.
Flash ROM
The ROM is the M-System DiskOnChip, with embedded thin flash
controller and flash memory on a single die. It has a capacity of 128 MB (1
GB) and a 2 Kbyte programmable boot block. This block provides eXecute
In Place (XIP) functionality, enabling DiskOnChip to replace the boot
device and function as the only non-volatile memory device on board.
Major Function Blocks of the Controller
Ethernet Controller
The Ethernet controller LAN91C111 is a 3.3 V single chip, consisting of
three indexing address lines and sixteen data lines. These buses will be
routed through transceivers for signal level conversion. The main chip
addressing is handled by the chip select from the processor through the
transceiver (nETH_AEN).
The chip supports both the 10 and 100 Mbps speed. Two different
interfaces are supported on the network side. The first interface is the
standard Magnetics transmit/receive pair interfacing to 10/100 BaseT
utilizing internal physical layer block. The second interface follows the MII
(Media Independent Interface) specification standard.
Both the isolation transformer and the standard RJ45 connector reside on
the I/O board. The transmit and receive signals are routed through an
internal wire harness from the MLB board to the I/O board. Both the
transmit and receive signal lines are differential pairs.
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